DS280DF810: PRBS

Kai Hsiao

Guru 12675 points

Other Parts Discussed in Thread: DS280DF810, DS280DF810EVM

rt Number: DS280DF810

HI Sir

1. When I use PRBS15 pattern input DS280DF810EVM ,the CDR can't locked

Do you have idea about this issue ( PRBS15 Pattern as attached file)

2. Have any register can disable CTLE and VGA function? I would like to bypass CTLE and VGA function without any EQ or something else

3. May I know below register address ?

over 7 years ago

0 Lee Sledjeski over 7 years ago

TI__Mastermind 43795 points

Hi Kai,

1. What is the datarate? The oscilloscope also seems to be having a problem to understand the input signal.

2. The CTLE minimum gain is Boost = 0

3. The EQ Gain bit is channel register 13[5]; The VGA Gain bit is channel register 0x8E[0]

Regards,

Lee

0 Kai Hsiao over 7 years ago in reply to Lee Sledjeski

Guru 12675 points

HI Lee

1. PRBS15=10.3125Gbps

Below is PRBS15 (can't lock)

Sinewave (can be lock)

2. I saw the min gain is 9.2dB

0 Lee Sledjeski over 7 years ago in reply to Kai Hsiao

TI__Mastermind 43795 points

Hi Kai,

In a previous graphic the Sigcon Architect page was not set to 10.3125 Gbps. Please verify you have programmed the DF810 to lock to this datarate.

Regards,
Lee

0 Kai Hsiao over 7 years ago in reply to Lee Sledjeski

Guru 12675 points

HI Lee

You mean here , is it right ?

0 Lee Sledjeski over 7 years ago in reply to Kai Hsiao

TI__Mastermind 43795 points

Hi Kai,

The sinewave is ~ 3GHz according to the oscilloscope. This would not lock using the 10.3125 Gbps rate selection.

Regards,

Lee

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DS280DF810: PRBS