TLK110: when tlk110 work under rmii mode, is pin 6(TXD_3) must have an external 2.2kohm pulldown resistor

Hi user,

I would suggest building a loopback cable to see if the TLK110 can connect to itself.

If it can, then you have an issue with either your register settings or your reference clock.

I do not see a problem with your registers at the moment. Please build an RJ45 loopback cable and see if your TLK110 design can link up in loopback mode.

www.juniper.net/.../fe-ge-loopback-plug-rj-45.html

Best Regards,

Hi Rodrigues:
Thanks for you suggestion. Here is a problem about the ETH_RMII_REF_CLK, when using RMII mode, this clock should be 50MHz. But this clock is about 4.3MHz. The XI pin (34) clock is from MCO2, which is coming out from stm32f429 and the clock is 50MHz. Where is this bug from?
My initialization sequence is:
1. Reset the 29 pin. This pin can controlled by MCU.
2. wait for 10ms.
3. write register 0x00 with 0x8000
4. write register 0x1F with 0x0800
5. wait for 10ms.
6. read register 0x01, waiting bit 2 indicate a valid link established.
7. write register 0x00 with 0x1000 to enable auto-negotiation.
8. read register 0x01, waiting bit 5 indicate auto-negotiation complete.
9. read register 0x10 to get the status.
but step 6 is wrong, the register 0x01 is always 0x7849, which indicate non-valid link established. Is my initialization sequence OK?
Thanks.

Hi Rodrigues
Another question, Is the RMII_REF_CLK coming from the tlk110 and send to MCU? Thanks.

Dear Rob:
        Using an RJ45 loopback cable, I can get a valid link and ETH_RMII_REF_CLK is 50MHz. But using a real cable whether if this cable is MDIX or MDI, tlk110 can not make a valid link and ETH_RMII_REF_CLK is about 4.3MHz. I also try to write register 0x09 to value 0x7C61 and set register 0x19 bit 15, but it is useless. The phy sch is below:

So what is the wrong? Thanks.

      I also have a design under tlk110 datasheet page23 figure 4-2, the phy sch is below:

    In this mode, using an RJ45 loopback cable, I can not get a valid link.

Thanks.

Hi,

You said above that the reference clock is 4.3MHz. This PHY requires a 50MHz clock as specified in the datasheet.
Please supply the PHY a valid reference clock.

Dear Ross
The PHY reference clock is 50MHz. using an RJ45 loopback cable, I can establish a valid link and the ETH_RMII_REF_CLK is 50MHz. But using a real cable, I can not establish a valid link and ETH_RMII_REF_CLK is about 4.3MHz.
Where is the problem.
Thanks.

Dear Rose:

According to tlk110 datasheet page8 pin 39(RX_DV),

I add a pull-up resistor, the whole tlk110 sch like bleow

In this mode. RJ45 loopback cable, real RJ45 cable both can establish a valid link. But a very strange thing happens, tlk110 pin 38(RX_CLK) is 25MHz. In RMII mode, the pin 38(RX_CLK) shold be 50MHz? 

So what is the problem? and using RMII mode, tlk110 pin 39 must have a pull-up resistor?

Thanks.

Hi,

It sounds like there is an issue with the processor.
The PHY does not control the external clock source.

RX_CLK will output a 25MHz clock in 100Mbps operation and a 2.5MHz clock in 10Mbps operation.

Dear Ross
You mention MII_MODE strap, is this write register 0x17 bit 5?
Thanks.