DS90UB928Q-Q1: Question about Power up sequence

Hello Nobuo,

For the Q1, PDB pin can be brought high after all VDD pins have settled within their recommended voltage ranges. There is no specific PDB rise time (tdly) requirement. The minimum delay from all VDD pins settled to PDB high is 0ms.

For the Q2, PDB needs to be high for minimum 1ms before a hard reset. The hard reset time (PDB low time) should be at least 2ms.

Regards,
Davor