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DP83822IF: RMII timming sequence of DP83822IF

Sulyn ZHANG
Expert 8700 points
Part Number: DP83822IF

Team,

We are now fan-out DP83822 in more projects in my customer. For the new project, they plan to use FPGA and RMII interface of our DP83822. As this is first time they use FPGA to connect DP83822 with RMII interface, they hope we can help provide some timing sequence for RMII interface, so they can do the program based on the timing sequence, so do we have this document or guide book for customer to use? Thanks a lot!

Best regards,

Sulyn

  • 0
    TI__Mastermind 23675 points
    Hi Sulyn,

    Have you had a look at the power-up/reset timing diagrams in the DP83822 datasheet?
    Will the customer be doing hardware bootstrap configuration or register access configuration using MDIO/MDC?
    They can power the DP83822 into RMII without the need for firmware.
  • 0 in reply to Ross Pimentel
    TI__Expert 8700 points
    Hi Ross,
    Thanks for the support. Customer can read/write registers by using MDIO/MDC interface. This no problem and DP83822IF is configured to RMII interface. However, as for the RMII interface, because customer use FPGA, so they need to write code to realize RMII MAC interface, thus they want to know if they need to know the timing of these pins: TX_EN, TX_D[1:0], RX_D[1:0], CRS_DV .etc . So not sure my understanding is correct or not?
    It will helps if you can share some helpful suggestion, thanks a lot!

    Best regards,
    Sulyn
  • 0 in reply to Sulyn ZHANG
    TI__Mastermind 23675 points
    Hi Sulyn,

    I am sorry, maybe I am not fully understanding the question.
    They want the FPGA to detect that the PHY is in RMII? They can read register 0x17 to see if the PHY is in RMII.

    Those pins are defined in the datasheet and I will not list our each function since its documented there.
  • 0 in reply to Ross Pimentel
    TI__Expert 8700 points

    Ross,

    Sorry again if confusing, it's easy to use the MDIO/MDC interface to read or write the registers and know the PHY is RMII interface. However, as these is digital signal on these pins: TX_EN, TX_D[1:0], RX_D[1:0], CRS_DV .etc when DP83822 working at RMII interface. Thus these should be some timing sequence or protocol for these pins, so customer need to know this and program the FPGA to communicate with DP83822(Not through MDC/MDIO but through RMII interfaces), I'm not sure is this clear? Thanks.

    Best regards,

    Sulyn

  • 0 in reply to Sulyn ZHANG
    TI__Mastermind 23675 points
    Hi Sulyn,

    I am not sure I follow. Sorry about this.

    The customer wants to know if they PHY is in RMII? Will they be supplying a 50MHz reference clock or will the DP83822?
    If you configure the DP83822 to RMII Master mode, the DP83822 will output a 50MHz reference clock on RX_D3 that need to be fed to the MAC.
    Maybe they should use this method for what they are trying to do?
  • 0 in reply to Ross Pimentel
    TI__Expert 8700 points
    Hi Ross,
    Customer already confirm they are using RMII mode of DP83822 and this is no problem! Because they need to connect TX_EN, TX_D[1:0], RX_D[1:0], CRS_DV .etc these related RMII pins to FPGA's pins. So they want to know if these is timing sequence on TX_EN, TX_D[1:0], RX_D[1:0], CRS_DV .etc these pins? So they can follow the sequence to program FPGA.

    Best regards,
    Sulyn
  • 0 in reply to Sulyn ZHANG
    TI__Mastermind 23675 points
    Hi Sulyn,

    TX_EN will should be asserted along with valid data on TX_D[1:0]. TX_EN and data will be in relation to the RMII reference clock.
    TX_EN must remain high for the entire valid frame transfer.
    For CRS_DV, this is an asynchronous pin and will be asserted when a frame is detected on the line. You can also use RX_DV pin to more easily recover the actual frame.

    In our datasheet you can see the timing requirements on setup and hold.