Other Parts Discussed in Thread: TAS5760M,
Hi everyone!
We are building device consisting DS90UB948-Q1 deser. IC, and 2-channel D-class power amplifier TAS5760M with a I2S interface.
As it mentioned in TAS5760M datasheet, we have to connect I2S interface in a such way:
1. MCLK (Master Clock)
2. SCLK (Bit Clock)
3. LRCK (Word Select Clock)
4. SDIN (Data Line)
At the other end, at deser. we have 9 pins, that are belong to I2S interface.
Power Amp works only in slave mode, so we have to use deser. as a master I2S source.
Our suggestions, that we have to use pins in a such way:
DS90UB948 -> TAS5760
1. MCLK -> MCLK
2. I2S_CLK -> SCLK
3. SWC -> RLCK
4. SDOUT -> SDIN
But, I2S_CLK mentioned in datasheet, as a Slave mode pin...
And, another one point, that we have pins I2S_DA and SDOUT as a data pins.
Please, check our decision for correctness.
