DP83867CS: Ethernet is not working at 1000Mbps speed where as other speeds it is working, need help on BIST too

Hi Geet,

Thank you very much for your quick reply.

Please find my reply in line

Geet Modi said:

Hi,

Below logs indicate communication with your Link Partner is not happening properly.

a. Have you reviewed your hardware schematics ? Can you share for me to look at ?

Yes we got the schematic reviewed. Please find the attached schematic.5751.rpcoc-bb-ti-review.pdf

b. IO voltage supported are 3.6/2.5/1.8. At 2.7V you are at violating the spec.

VDDIO voltage is brought up due to I/O voltage requirements from ZYNC7000 processor. This was earlier 3.3V, but due to warning brought out by Zync that RGMII may not work at 3.3V, we have to change that to 2.7V. This changes we have verified with TI here

But just to bring to your notice, working phy has also same design.

The Phy is working at 10Mbps/100Mbps, can this mean Tx/Rx lines that line 4,5,7 or 8 which are not part of 10/100Mbps by 1000Mbps can have interface issue?

Regards.
Geet


Register 0x0A

1 > Manual Master/Slave Configuration fault detected.

2 > Local receiver is not OK.

3 > Remote receiver is not OK.

4 > Link partner not capable of 1000Base-T Full Duplex.

5 > Link partner not capable of 1000Base-T Half Duplex.
Please note that both the phys are DP83867CRto be configured in RGMII interface.

Hi Geet,

We are using a switch for connecting both Phys. We interchanged ports between phys and also we changed cable.

Can you please let me know whether BIST will be helpful to debug? If yes then what is the procedure. I didn't found steps for performing BIST, but I tried the way I interpreted from datasheet.

Can line number 4,5,7 or 8 on RJ45 be an issue?

Hi,

I don't know what do you mean by BIST from Ethernet Phy point of view. We have internal loopback test available but not sure how they can help in this scenario ?

Given both phy schematics are exactly same, suggest you look out for assembly or routing differences between two.

Can you try connecting two Phy with each other thru a cross cable ?

Regards,

Geet

Hi Geet,

BIST is Built In Self Test where pseudo random packets are generated in different loop-back setup and error bytes are counted

BIST is one of diagnostic method presented here. This can help us at which point phy has error.

Our hardware team has verified routing and assembly aspect, any way we have plans to test the same thing with different spin of the board but that may take some time

We will connect both phys test as you suggested, but I am unclear how may it will be helpful.

Just to clarify, are there any concerns when more than one phys are connected.

One more point to be noted is, MDIO/MDC lines of both phys is connected to MAC that is working. i.e GEM0, can it cause issue.

Can we suspect TX/RX lines which are not in picture for 10/100Mbps??

Is RGMII receive/transmit delay have role to play in this issue?

Thank you for help

Regards,

Abhijit

Hi Geet,

There is very less documentation on BIST available on net. As mentioned earlier I tested with BIST but it is showing error at 10/100Mbps too, which is supposed to be working case. Can you please verify register write sequence in the pseudo code that is shared with you? or as this is inherent and important feature, TI must have used it and there may be flow diagram available with TI, can you share such docs?

/* Set RGMII mode */
reg_val = REGR16(DP_RGMIICT); 
reg_val |= (1 << 7);
REGW16(DP_RGMIICT, reg_val);

/* Set MDI mode manually */
reg_val = REGR16(DP_PHYCR);
if (mdix == 0) {
    printf("Setting MDI connection manually\n");
    reg_val &= ~(3 << 5);
} else { 
    printf("Setting MDIX connection\n");
    reg_val &= ~(3 << 5);
    reg_val |= (1 << 5);
}
REGW16(DP_PHYCR, reg_val);

/* Set-up BMCR */
reg_val = REGR16(DP_BMCR);

/* Set-up speed */
printf("Speed: ");
switch (speed) {
    case 1000:
        printf("1000BaseT\n");
        reg_val |= (0x1 << 6); /* Set 1000BaseT*/
        reg_val &= ~(0x1 << 13);
        break;
    case 100:
        printf("100BaseT\n");
        reg_val &= ~(0x1 << 6); /* Set 100BaseT*/
        reg_val |= 0x1 << 13;
        break;
    case 10:
        printf("10BaseT\n");
        reg_val &= ~(0x1 << 6); /* Set 10BaseT*/
        reg_val &= ~(0x1 << 13);
        break;
};

/* Set-up auto negotiation */
printf("Autoneg : %s\n", auto_neg ? "ON" : "OFF");
if (!auto_neg) {
    reg_val &= ~(0x1 << 12); /* Disable auto-negotiation */
} else {
    reg_val |= (0x1 << 12); /* Enable auto-negotiation */
}

/* Set-up duplex type */
printf("Duplex : %s\n", duplex_type == full_duplex ? "FULL" : "HALF");
if (duplex_type == full_duplex) {
    reg_val |= 0x1 << 8; /* Full duplex */
} else {
    reg_val &= ~(0x1 << 8); /* Half duplex */
}

REGW16(DP_BMCR, reg_val);

/* Soft reset */
reg_val = REGR16(DP_BMCR);
reg_val |= 0x1 << 15;
REGW16(DP_BMCR, reg_val);

printf("Waiting for reset to complete ...\n");
do {
    reg_val = REGR16(DP_BMCR);
} while (reg_val & (1 << 15));

/* Wait for link training to complete */
printf("Link status 0x%x\n", REGR16(DP_PHYSTS));
printf("Waiting for link to be up ..\n");
while (!(REGR16(DP_PHYSTS) & (1 << 10)));

printf("BMCR 0x%x\n", REGR16(DP_BMCR));

/* PRBS count mode */
REGW16_FIELD(DP_BISCR, PRBS_COUNT_MODE, 1);

/* PRBS generate packet */
REGW16_FIELD(DP_BISCR, GEN_PRBS_PACKET, 1);

/* Disable PCS loop-back */
REGW16_FIELD(DP_BISCR, PCS_LOOPBACK, 0);

/* Non-PCS loop-back */
{

    switch(loop_back) {
        case BISCR_LOOPBACK_MODE_digital_loop:
            printf("Digital loop-back\n");
            break;
        case BISCR_LOOPBACK_MODE_analog_loop:
            printf("Analog loop-back\n");
            break;
        case BISCR_LOOPBACK_MODE_external_loop:
            printf("External loop-back\n");
            break;
        case BISCR_LOOPBACK_MODE_reverse_loop: 
            printf("Reverse loop-back\n");
            break;
    };

    REGW16_FIELD(DP_BISCR, LOOPBACK_MODE, loop_back);
}

printf("<<<<<<<<<<<<<<<<<<<< Reg dump >>>>>>>>>>>>>>>>>>>>\n");
printf("DP_PHYIDR1 0x%x\n", REGR16(DP_PHYIDR1));
printf("DP_RGMIICT 0x%x\n", REGR16(DP_RGMIICT));
printf("DP_PHYCR 0x%x\n", REGR16(DP_PHYCR));
printf("DP_RGMIIDCTL 0x%x\n", REGR16(DP_RGMIIDCTL));
printf("DP_BMCR 0x%x\n", REGR16(DP_BMCR));
printf("DP_BISCR 0x%x\n", REGR16(DP_BISCR));
printf("==================================================\n");

/* Enable packet generation */
REGW16_FIELD(DP_BISCR, PACKET_GEN_EN, 1);

/* Wait for lock to release */
do {
    if (REGR16_FIELD(DP_STS2, PRBS_LOCK) == 1)
        locked = 1;
    if (--count == 0) {
        break;
    }
} while (!locked);


if (REGR16_FIELD(DP_STS2, PRBS_LOCK_LOST) == 1)
    lost_lock = 1;

byte_cnt = REGR16(DP_BICSR1);

/* Stop and clear PRB counter */
REGW16(DP_BICSR1, 0x3);

/* In continous mode error is checked once packet generator is disabled */
REGW16_FIELD(DP_BISCR, PACKET_GEN_EN, 0);
err_byte_cnt = REGR16_FIELD(DP_BICSR2, PRBS_ERR_CNT);

if (REGR16_FIELD(DP_STS2, PKT_GEN_BUSY) == 1)
    busy = 1;

printf("Busy bit 0x%x, Locked status 0x%x\n",
            REGR16_FIELD(DP_STS2, PKT_GEN_BUSY),
            REGR16_FIELD(DP_STS2, PRBS_LOCK));

locked = REGR16_FIELD(DP_STS2, PRBS_LOCK);
if (locked)
    printf("Locked\n");

if (busy)
    printf("Busy\n");

if (lost_lock)
    printf("lost lock\n");


printf("Byte count %d Error byte count %d\n", byte_cnt, err_byte_cnt);

Hi Geet,

Sorry for delay in response.

Please find the register write sequence for BIST test where both working phy(At address 3) and non-working phy(At address 2) are connected with straight cable.

PRBS are enabled for both phys and Error count and byte received are printed only for phy at address 2

One more point to note that, we are able to perform sample example from Xilinx for loop-back with MII loop-back, but same fails if we do digital loop-back. i.e BISCR |= (1 << 2). Please let know why this behavior even when we are following sequence in data sheet. Even for working Phy the loop-back fails

Can you please confirm sequence for digital loop-back? I have very high hopes with TI to help in solving such trivial issue.

Hi Abhijit,

Can you confirm the following indications in your usecase:
1. Link status of non working PHY? Can you read 0x0011?
2. RX_CLK frequency on RGMII I/F of non working PHY?
3. TX_CLK clock frequency from the MAC?
4. Strap configuration status registers (Read 0x006E and 0x006F) on both the PHYs

Can you also try the following procedure:
1. Connect the DUT1 to DUT2 through CAT5e cable. Check whether link is up in 1000M mode (0x0011 = 0xBC02/0xAC02)
2. Enable reverse loopback on DUT2 (0x0016 = 0x0020). No need of other configurations for reverse loopback
3. Start packets on the MAC of DUT1
4. Check if there are any errors in the packets received back after loopback

You can then swap the functionalities (Packets from DUT2 and reverse loopback on DUT1 ) and check
This will ensure the proper functionality of MAC and MDI interfaces on both the PHYs at 1G speed.

Regards,
Anmol