DS110DF410: About HEO_VEO_INTERRUPT register/0x30[4]

Toshiyuki

Part Number: DS110DF410

Hi,

I'd like to confirm about HEO_VEO_INTERRUPT register/0x30[4]. Is there a possibility that the register become 1 while any signal don't input and CDR hasn't achieved lock ?

Best Regards,

Toshiyuki

over 7 years ago

0 Toshiyuki over 7 years ago

Mastermind 7075 points

Please let us know the current status regarding this thread.

0 Michael Lu (Santa Clara) over 7 years ago in reply to Toshiyuki

TI__Mastermind 29655 points

Hi Kato-san,

Sorry for the delay. We're looking at this and will respond by the end of today.

Thanks,

Michael

0 Michael Lu (Santa Clara) over 7 years ago in reply to Michael Lu (Santa Clara)

TI__Mastermind 29655 points

Hi Kato-san,

Yes, it is possible for the interrupt bit to become 1 when CDR lock is lost or the signal. I would advise that, since this bit is sticky, the customer should verify the device is locked first (with HEO_VEO_Interrupt Read-back = 0), then read-back HEO_VEO Lock Interrupt Threshold to determine whether a HEO/VEO_Interrupt is related to loss-of-lock or due to the HEO/VEO eye opening criteria.

Regards,

Michael

0 Toshiyuki over 7 years ago in reply to Michael Lu (Santa Clara)

Mastermind 7075 points

Hi Michael - san,

Thank you for your support. Our customer has another question for HEO_VEO_INTERRUPT bit. I understand the bit is cleared after reading. Then, whenever the bit is read while the HEO/VEO values are below the limits set in channel register 0x76, does the HEO_VEO_INTERRUPT read back High(=1) at all time ?

Best Regards,

Toshiyuki

0 Michael Lu (Santa Clara) over 7 years ago in reply to Toshiyuki

TI__Mastermind 29655 points

Hi Kato-san,

The HEO/VEO interrupt will go high (= 1) at the moment of the first interrupt after this interrupt bit is enabled. Afterwards, it will remain this way until read back. Therefore, even though the HEO/VEO values may fall below the interrupt limits after the interrupt asserts for the first time, the HEO_VEO_INTERRUPT bit will remain High until the bit is read-back.

Regards,

Michael

0 Toshiyuki over 7 years ago in reply to Michael Lu (Santa Clara)

Mastermind 7075 points

Hi Michael - san,

I'm understanding as shown below. Is this correct ?

Best Regards,

Toshiyuki

0 Michael Lu (Santa Clara) over 7 years ago in reply to Toshiyuki

TI__Mastermind 29655 points

Hi Kato-san,

This is almost correct!

The portion where you measure "Low(=0)" in your diagram will actually still be "High (=1)." This is because this is the first read-back of the HEO_VEO_INTERRUPT status after the HEO/VEO values crossed underneath the interrupt threshold. If you were to read back HEO_VEO_INTERRUPT a 2nd time after the HEO/VEO value remains below the interrupt threshold, then I would expect to read-back "Low(=0)."

Thanks,

Michael

0 Toshiyuki over 7 years ago in reply to Michael Lu (Santa Clara)

Mastermind 7075 points

Hi Michael - san,

I understand. Thank you for your perfect explanation.

Best Regards,

Toshiyuki

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DS110DF410: About HEO_VEO_INTERRUPT register/0x30[4]