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DS100BR410: failure modes question

Karrie Dooley
Prodigy 20 points
Part Number: DS100BR410

Support Path: /Product/Development and troubleshooting/

I am looking at the failure modes of the DS100BR410. Can someone tell me what happens on the I/O pins if the input to the 2.5 I/O Voltage goes well above the absolute maximum rating? In other words, will a power supply failure propagate through the part?

  • 0
    TI__Mastermind 29655 points
    Hi Karrie,

    If the input far exceeds the 2.5V I/O voltage max rating (beyond 2.75V), and the device is operated while exposed to this high voltage, the life of the part will degrade, and the reliability of the DS100BR410 can no longer be assured. To avoid a power supply failure, it is typical to use an LDO prior to the power supply to ensure that the DS100BR410 receives a consistent 2.5V.

    Note that the above statement assumes sustained exposure in operating mode, rather than an ESD event as defined by the ESD Rating also provided within the Absolute Maximum Ratings table.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 20 points

    Michael,

    Thank you for the response. However, the information provided does not answer my question. I understand that the life of the part will degrade and that's exactly what I'm worried about. I am working with an as built design and have no ability to change it to include protections. I need to know how the part will fail. Can you tell me what the failure mechanism is for an overvoltage and specifically if the input voltage will be seen on the output pins? Also, is the part cold spared? Meaning, is it acceptable to have an input on the pins when the part is unpowered?

    Thanks.

  • 0 in reply to Karrie Dooley
    TI__Mastermind 43795 points

    Hi Karrie,

    The input voltage will not be seen on the output.

    The most likely failure mechanism is a degradation in bipolar transistor beta or gain.  There are also CMOS circuits which would be subjected to the increased voltage levels.  For CMOS gate oxide failures will eventually occur if the voltage is high enough.

    If the device GND is in place it is okay to apply a signal to the inputs.

    Regards,

    Lee