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DP83867E: Full control of the packet lengths and of the IPG in BIST mode?

Part Number: DP83867E

Section 8.4.5 of the datasheet states "The BIST allows full control of the packet lengths and of the IPG." I can find a bit field PACKET_GEN_64BIT_MODE in BIST Control Register (BISCR) which offers at least some (not full..) control of the packet lengths, but which register allows (full) control of the IPG?

  • Hi Roel,

    The sentence you have quoted is not entirely clear as you only get control of the IPG on the BIST packet generator. In the last sentence of the following paragraph, you can read this for the packet size "Packet transmission can be configured for one of two types, 64 and 1518 bytes, through register bit 13 of the BISCR register (0x0016)."

    The IPG control is done through register address 0x7C.

    Bit[7:0] controls the IPG, in bytes. Default of this register is 0x7D, corresponding to 125 byte IPG.

    It is not suggested to use values below 0xC, which is 12 bytes IPG, the minimum for Ethernet.

    Best Regards,
  • Hi Rob,

    I did some tests with the IPG setting. It looks like the IPG number that is set is multiplied by 4. If I increase the IPG by one I get 32ns extra delay.

    I get the pattern generator working, and I can nicely use it for SFD signal generation. However, I don't understand the length of the SFD high period. The master SFD high time is always 12us, which suggests I have a ~1500byte packet (assuming the SFD is 1 until the end of the Ethernet frame). Setting the bit 13 of BISCR doesn't seem to affect the high time. I looks like the packet is always 1518bytes. What could be wrong? How do I get 64 bytes frames?

    Best Regards,

    Roel

  • Hi Roel,

    Register 0x7B sets the PRBS length in bytes. Default is 0x5DC, which is 1500 bytes.

    Best Regards,