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Address Pin(EEPROM) Setting for DS100DF410

Hidekazu
Intellectual 880 points
Other Parts Discussed in Thread: DS100DF410

Hi Everyone

Referring to Figure 5 in the DataSheet(www.ti.com/.../snls399b.pdf),
A1 and A2 of the EEPROM are floating,
but looking at Snla245(www.tij.co.jp/.../snla245.pdf), A0 and A1 is floating.

Which one is correct?

By the way, the evaluation board seems to be designed based on Snla245.

Best Regards,
Honma

  • 0
    TI__Mastermind 29655 points
    Hi Honma-san,

    The choice of floating A0, A1, or A2 depends on the EEPROM size and whether the voltage on these pins is used for addressing the EEPROM. Both the DS100DF410 datasheet Figure 5 and SNLA245 Table 5, 6 are valid.

    Please look in more detail at Table 5 and 6 to see whether the EEPROM Device Addressing for the EEPROM you choose is set by pin logic on A0-A2 or if device paging is used instead. If device paging (P0-P2 instead of A0-A2) is used to set the address Bits [3:1], then the corresponding A0-A2 pins are ignored can be treated as no connect allowing you to leave the pin floating or tied low to GND, since they will default to logic "0".

    For simplicity, I suggest always tying A0-A2 pins to GND. This way, if you choose to use a small EEPROM size (for example, 2K size), then the 7-Bit EEPROM Device Address is 0x50 since A0-A2 are tied to GND. If you choose to use a larger EEPROM size (for example, 16K), then the 7-Bit EEPROM Device Address still defaults to 0x50, but since Bits [3:1] are used for page addressing, the actual voltage applied to A0-A2 pins is ignored.

    Which EEPROM are you planning to use?

    Thanks,

    Michael