DS90UB948-Q1: ds90ub948 GPIO Function

Lingying,
do you have waveform for it? also, how about the PWM rate?
best regards,
Steven

Hi Steven,

The input PWM=1.8V, EN=1.8V, the output is changed from frame rate. Different frame rate, different PWM and  EN waveform.

Frame rate=20Hz

Frame rate=40Hz

Frame rate=60Hz

best regards,
Lingying

Lingying,
from the test plots, it seems UB948 has no PWM output at 20fps but can work at 40fps and 60fps, correct?

if yes, please check the PCLK freq. and PWM pulse width? in general, the PWM pulse should be much large than the PCLK period time, thanks.

best regards,
Steven

Hi Steven,
Yes.
PWM is high and the LOCK signal is same as PWM and EN.

best regards,
Lingying

Lingying,
which channel is LOCK signal?
please secure that the PWM pulse is much less than the PCLK period.

best regards,
Steven

Hi Steven,
Channel 2 and channel 3 are PWM and EN output of DS90UB948, the PWM and EN input of DS90UB947 is always high.
The LOCK signal is same as PWM and EN output of DS90UB948.

best regards,
Lingying

Lingying,
Lock is same as ch2 & ch3? it means the link is NOT stable, in most time the link is un-locked. please check your link design, such as cable? connector? PCLK? Power design? etc.

best regards,
Steven

Hi Steven,

      I meet the same problem.Our resolution is 1920*720,When I set the frame rate=20hz,PCLK=14Mhz, the display works well and the lock is high. When i set the frame rate =60hz,PCLK=44M,

the display is blinking and the pwm,en,lock are the same wave which have falling edge quickly like lingying's picture.

with higher PCLK frequency, the data rate is higher as well (proportional). so please check the link signal integrity in your case.
for details, you can check the www.ti.com/fpdlink for on-link video training on high speed channel design points, thanks.

best regards,
Steven

Hi  Steven，

       When I set Frequency=50Mhz, the display is work well. And I found some frequency work well and some work bad.NO matter Frequency is high or low.      

not, we don't meet any such issue in UB947 device. please check whether the SoC who sends data to UB947 is workable or not if you change any freq. for debugs? also, please list detailed freq. points if you have issue. if possible, please measure the PCLK jitter on UB947's LVDS clock input pins, also please measure the CMLout signals in the UB948 side. this action is to help check whether the input to UB947 and the link between UB947 and UB948 is specified or not.

best regards,
Steven