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DS90UH928Q-Q1: delay time of LVDS output when LOCK is asserted/de-asserted

Ryuuichi machida
Guru 12185 points
Part Number: DS90UH928Q-Q1

Hi,

I would like you to confirm about following time.

Could you please confirm about this ?

Best Regards,

Machida

  • 0
    TI__Intellectual 2010 points

    Hi Machida,

    I will test the time in lab and give you the answer by the end of this week.

    Best regards,

    Cera

  • 0 in reply to Cera Wei
    Guru 12185 points

    Hello Cera-san,

    Thank you for your reply.

    >I will test the time in lab and give you the answer by the end of this week.

    Also, we also would like to know delay spec for DS90UB914A and DS90UH948.

    Could you test for above additional two devices as well ?

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points
    Sure, I will do that.

    Best regards,
    Cera
  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points

    Hello Machida,

    Here's the update:
    I tested 948 delay spec using 948/947 pair. The clkout delay after lock asserted is 106ns. The clkout gets zero immediately when 948 lose lock, that is the delay is zero.

    Best regards,
    Cera

  • 0 in reply to Cera Wei
    Guru 12185 points

    Hello Cera-san,

    Thank you for your reply.

    >The clkout delay after lock asserted is 106ns. The clkout gets zero immediately when 948 lose lock, that is the delay is zero.

    I want to confirm about environment of measurement.

    In case of "lock asserted", I also confirmed similar result, however, in case of "lose lock", I observed different result.

    (949/948 pair, Green : LOCK, Yellow : CLK0+, Blue D3-)

    Could you please tell me which potion did you measure ?

    BR,

  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points
    Hello Machida,

    I used 947EVM and 948 EVM with STP cable, and used pattern generator on 947 for input. Set 948 Reg 0x34[7] =0 to configure RX_LOCK asserted only when receiving active video.
    When disable the pattern generator, it will lose lock and CLK would go to zero.

    Best regards,
    Cera
  • 0 in reply to Cera Wei
    Guru 12185 points

    Hello Cera-san,

    >I used 947EVM and 948 EVM with STP cable, and used pattern generator on 947 for input. Set 948 Reg 0x34[7] =0 to configure RX_LOCK asserted only when receiving active video.
    >When disable the pattern generator, it will lose lock.

    I performed same way. Difference is only SER device(I used 949).

    Maybe, something was different, but important thing is "unit" when lock is asserted and lock is lost. So, your result may be fine.

    BTW, I confirmed delay time for DS90UB914A. Then, I got following result.

    (Yellow : PCLK, Green : LOCK Blue : VSYNC)

    This result is strange, because PCLK  is active before LOCK is asserted.

    Could you please confirm about DS90UB914A at first and confirm whether you also got same result or not ?

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points
    Hello Machida,

    Sorry to reply late. I tested the 914 timing and got the same result. We are now trying to figure out the reason.

    For 928 part, the PCLK output delay after lock is 216ns. And the PCLK output gets to zero immediately after lose lock. The test condition is:
    Use 925/928 pair;
    Digital reset 928 to trigger lock and unlock.

    Best regards,
    Cera
  • 0 in reply to Cera Wei
    Guru 12185 points
    Hello Cera-san,

    Thank you for your reply.
    I understood delay time for 928/948.

    >Sorry to reply late. I tested the 914 timing and got the same result. We are now trying to figure out the reason.
    Thank you for your response.
    This behavior does not follow datasheet (According to datasheet, CLK and DATA should be "L" until LOCK is deasserted), so please keep to investigate.

    Best regards,
  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points

    Hello Machida,

    For 914, the lock signal is generated differently in different mode. It is verified that in 12LF and 10bit mode, PCLK will become active before LOCK output. In 12HF mode, they go active at the same time. We will update the datasheet later.

    Best regards,
    Cera

  • 0 in reply to Cera Wei
    Guru 12185 points

    Hello Cera-san,

    Thank you for your confirmation !

    Actually, I observed difference b/w "12 bit HF" and "12bit LF, 10bit mode".

    >they go active at the same time.

    However, in case of 12 bit HF, I can observe approximately 3 us delay as shown below.

    1. Is it not expected result ?

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points

    Hi Machida San,

    It should be alerted at the same time according to design's simulation. I will double check it.

    Best regards,

    Cera

  • 0 in reply to Cera Wei
    Guru 12185 points
    Hello Cera-san,

    Do you have any update ?

    Best Regards,
  • 0 in reply to Ryuuichi machida
    TI__Intellectual 2010 points
    Hi Ryuuichi-san,

    I tested 913/914 at 12bit HF mode, and the result is the same with you, about 3us delay. The design simulation data is not zoomed in, so it looks at the same time.

    Best regards,
    Cera