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TPS65982: DPSourceSink bit behavior on 0x5F Data Status

Takashi Onawa
Genius 13200 points
Part Number: TPS65982
Other Parts Discussed in Thread: TPS65981EVM, HD3SS460, TPS65981

Hi Team,

Could you tell me how DPSourceSink bit behaves?

I checked DPSourceSink bit behavior using TPS65981EVM with following condition. But the bit always shows 0b "DP Source (DFP_D) connection requested" on both DFP_D and UFP_D sides. Is this bug?

①　TPS65981_HD3SS460_DRP_Source_Advanced_v3_10.tpl
②   TPS65981_HD3SS460_DRP_Host_Advanced_v3_10.tpl

[① Side]

[② side]

My customer is expecting that EC can judge PD controller is in UFP_D Assignments E condition by the table below. But it is not realizable because DPSourceSink is always 0b.

Regards,

Takashi Onawa

  • 0
    TI__Genius 10370 points

    Hi Takashi,

    Instead of using the DRP template, could you try setting on of the EVM boards as a DFP and the other as a UFP. This might fix the issue.

    ①  TPS65981_HD3SS460_DFP_Advanced_v3_10.tpl

    ②   TPS65981_HD3SS460_UFP_Advanced_v3_10.tpl

    If this answers your question, PLEASE select  This resolved my issue. 

  • 0 in reply to Aramis P. Alvarez
    TI__Genius 13200 points
    Hi Aramis-san,

    I checked DPSourceSink bit using DFP andUFP only FWs but It was not workaround.
    DPSourceSink bit has still showed 0b and I haven't seen any differences between DFP FW.

    If the PD controller is running as a UFP, Which value should be observed on this register, 0b or 1b?
    The explanation on Host interface Guide is very unclear.

    DPSourceSink[0x5F, bit9]
    0b DP Source (DFP_D) connection requested (if supported by configuration).
    1b DP Sink (UFP_D) connection requested (if supported by configuration).

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Genius 13200 points
    Hi Aramis-san,

    Could you give me a comment for my update and question above?

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Genius 10370 points

    Hi Takashi-san,

    Could take a look at the DP SID status register (0x58)? This register will tell the user if the PD Controller has entered DisplayPort Mode with attached UFP, DFP, or none.

    If this answers your question, PLEASE select  This resolved my issue. 

  • 0 in reply to Aramis P. Alvarez
    TI__Genius 13200 points

    Hi Aramis-san,

    I'm asking about DFP_D and UFP_D, not _U. And my customer wants to know the device is running as UFP_D or DFP_D in DP alt mode.

    As far as I checked the DP SID Status(0x58) register, it seemed that "DP configure" information is not updated on UFP_U side after DP enter mode.
    Is not this the cause of ”DPSource or Sink” bit not working properly?
    Please ask that to FW team.

    Don't forget to follow my question below also...

    >If the PD controller is running as a UFP, Which value should be observed on this register, 0b or 1b?
    >The explanation on Host interface Guide is very unclear.

    >DPSourceSink[0x5F, bit9]
    >0b DP Source (DFP_D) connection requested (if supported by configuration).
    >1b DP Sink (UFP_D) connection requested (if supported by configuration).

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 13200 points
    Hi Aramis-san,

    Can you give me a comment on how to check if the device is running in DFP_D or UFP_D at least?

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Genius 10370 points

    Hi Takashi-san,

    A DFP_D is essentially DFP_U (same for the UFP). The DFP_D is a Downstream-Facing Port as specified in DP v1.4 and referred to as “DFP” in that Standard. Generally associated with a DP Source device, but may also be associated with a DP Branch device. The DFP_U is a Downstream-Facing Port, specified as “DFP” in USB Type-C Specification. Typically the ports on a host or the ports on a hub to which devices are connected. Same goes for UFP.

    I'm looking into the correct bit that should be set in register 0x5F. I should be able to respond by end of day tomorrow.

    Question: Is the PD controller with display port working properly (not looking at the debug tool)? Are you able to use display port on a monitor with your current configuration?

  • 0 in reply to Aramis P. Alvarez
    TI__Genius 13200 points

    Hi Aramis-san,

    I don't think DFP_D is essentially DFP_U.

    DFP_U must behave as "Initiator" at alt mode PD communication, so that's very important role but, DFP_U and  UFP_U may support a DFP_D, a UFP_D, or both a DFP_D and UFP_D depending on its DP capability, right?

    Although I read the standard("VESA DisplayPort Alt Mode on USB Type-C Standard") easily, the item of DP configure may not be displayed normally depending on the contents of communication. I re-checked DP status table as below, PD controller role may be confirmed from this.

    But, I didn't see any change on 0x5F, DPsource or sink bit as I mentioned before. I'll waiting your update on this.

    >Question: Is the PD controller with display port working properly (not looking at the debug tool)? Are you able to use >display port on a monitor with your current configuration?

    Yes, I can display my PC's DP output to a monitor through EVM's connected with Type-C cable. So, I believe that it's working well. But on the App configue tool,  I could not see which DP role is chosen on each EVMs as the picture above.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 10370 points

    Hi Takashi-san,

    I talked to the FW team and this is a bug in our GUI. The GUI will always display a 0b for the DPSourceSink register (bit 9). I filed a ticket for our FW team to fix. Thank you for catching this bug.

    Also, If this answers your question, PLEASE select  This resolved my issue. 

  • 0 in reply to Aramis P. Alvarez
    TI__Genius 13200 points

    Hi Aramis-san,

    Thanks for looking into this. I understood.

    Let me ask three questions in the end of this thread.

    1. When is the next FW which fixed this bug going to be released?

    2. What is the trigger for updating this status register(0x5f)? And Is the default value of this register 0x00?

    3. Which register values do the following registers refer to and display the results?

    ‐　DPPinAssignment
    ‐　DPSourceSink 
    ‐　DPConnection
    ‐　USB3Connection

    Please tell me in detail which bit of which register consists the values of Status register.

    As I mentioned before, My customer is just coding their FW for their EC and they are requiring the information above for High speed mux controlling. Especially, they are struggling to support UFP_D assignment E.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 10370 points

    Hi Takashi-San,

    Look below for my comments/answers to your questions in red:

    1. When is the next FW which fixed this bug going to be released?

    We try to release a new firmware patch once a quarter. Our team will try to release this fix by sometime in Q2 2018. 

    2. What is the trigger for updating this status register(0x5f)? And Is the default value of this register 0x00?

    For bit 9, currently, there is no trigger and the default value is 0b. This is what we will try to patch up on the FW side. 

    3. Which register values do the following registers refer to and display the results?

    ‐ DPPinAssignment

    ‐ DPSourceSink

    ‐ DPConnection

    ‐ USB3Connection

    Please refer to the TRM, which has all of the register names and values (Table 3-63 through 3-65): http://www.ti.com/lit/ug/slvuan1a/slvuan1a.pdf. 

    Please tell me in detail which bit of which register consists the values of Status register.

    I'm not sure if I understand your question. But if you would like to know the bits in the Status Register (0x1A) please refer to the TRM, link above.

    As I mentioned before, My customer is just coding their FW for their EC and they are requiring the information above for High speed mux controlling. Especially, they are struggling to support UFP_D assignment E.

    Since this is a new issue (Pin Assignment), please post this as a new thread so that we can close this thread. Thank you and I hope this helps. 

    If this answers your question, PLEASE select  This resolved my issue.  

     

  • 0 in reply to Aramis P. Alvarez
    TI__Genius 13200 points
    Hi Aramis-san,

    Thanks for your quick reply on this.

    Unfortunately, your comments for status register(0x5f) are not enough to satisfy the customer.
    For coding EC "Driver", It is necessary to understand "access timing" and "how to handle register".
    So they planed to use the following bits to get alt mode "Assignment" info and make EC control system.
    But the two points which I mentioned above are very unclear even in TRM.

    ‐ DPPinAssignment
    ‐ DPSourceSink
    ‐ DPConnection
    ‐ USB3Connection

    Anyway, I post other thread on this and discuss that there.

    Regards,
    Takashi Onawa