Hi all
Would you mind if we ask DP83822?
<Question1>
When RD+ and RD are inserted invalid data, will RX Error count( Receive Error Count Register (RECR)) increase?
Or, does RX Error Count mean that there is error between PHY and CPU(MAC I/F)?
<Question2>
In relation to <Question1>, depending on an incorrect action of TXD0, does Link loss occur?
About Link loss detection, isn't TXD0 relation to Link loss?
Kind regards,
Hirotaka Matsumoto