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DP83867IR: Unable to establish link between DP83867IR and switch

Daman Makhija
Prodigy 140 points
Part Number: DP83867IR


Hello .

I am facing interface issue with DP83867IRPAP PHY device.

Problem statement: Unable to establish link between this device and switch (moxa :EDSG205-1GTXSFP-T & D-Link : DGS-3100-24).

Observation:
1) PHY is configured for MII 100 BASE-TX_Full Duplex mode.
2) PHY interface of 100Mbps with PC is successful.
3) PHY interface with MOXA & D-Link switch is not able to estabelish a link.
4) Fast Link Pulses are present at Physical Layer of both end i.e. PHY as well as MOXA-swicth/D-Link Switch:
5) As per Clause 28 of Auto Negotiation
a) PHY FLP decoding is : 1000 0111 1000 0000
b) MOXA-swicth FLP decoding is : 1000 0111 1011 0001

I am attaching the circuit for reference . PHY_Schematic.pdf

please do the needful to resolve the problem . 

Regards 

Daman

  • 0
    TI__Mastermind 19780 points
    Hi Daman,

    The DP83867IRPAP RX_DV/RX_CTRL pin MUST be strapped to mode 3. if you do not strap to mode 3, it is possible to have a problem with link stability with certain link partners.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 140 points
    Hi Rob ,

    Please refer to the schematic attached . As the board is already designed , Strapping option is not available in the schematic . How it can be done now ?

    Regards ,

    Daman
  • 0 in reply to Daman Makhija
    TI__Mastermind 23675 points

    Hi Daman,

    I will need to check with my team if there is any possible register workaround here.
    It is a key requirement to have the strap set to mode 3.

  • 0 in reply to Ross Pimentel
    Prodigy 140 points
    But in reference design also this option is not provided. We have done our schematic as per reference design and got verified by TI application engineer(india). But we were not told about this.
    Now what are the options available for us?
  • 0 in reply to Daman Makhija
    TI__Mastermind 23675 points
    Hi Daman,

    You can operate the PHY without the need for strap mode 3 by clearing bit[7] in register 0x31 after POR completes. For any subsequent RESET through RESET_N pin or register (0x1F), you will need to be sure that this bit is cleared.
  • 0 in reply to Ross Pimentel
    Prodigy 140 points
    Hello . We are not able to find this register 0x31 . Please tell the name of the register. Note - we have read the status of BMCR reg . In that auto negotiations duplex mode is on but Link is not establish .
  • 0 in reply to Ross Pimentel
    Prodigy 140 points
    Hi rob, i am not able to locate register 0x31, can you tell the name of register.
  • 0 in reply to Daman Makhija
    TI__Mastermind 23675 points
    Hi Daman,

    It is a hidden configuration. However, register 0x31 is in the DP83867IR.
  • 0 in reply to Ross Pimentel
    Prodigy 140 points
    Hello
    Configuration register 4 (CFG4) 0x0031 bit 7 is reserved having only read control. There is no write control . So what we have to do?
    Daman
  • 0 in reply to Daman Makhija
    Prodigy 140 points
    Waiting for the response...
  • 0 in reply to Daman Makhija
    TI__Mastermind 23675 points
    Hi Daman,

    Have you tried writing to register? Even though it says RO in the DS, it still can be configured.
    Please configure the register after you power it up and then write 0x4000 to register 0x1F after.
  • 0 in reply to Ross Pimentel
    Prodigy 140 points

    Hello Ross Pimentel

    We tried programming Register 0x0031 using register extended mode. The values we wrote in sequence are as follow :

    "5036001F" using REGCR ,

    "503A0031" using ADDAR,

    "5036401F" using REGCR,

    "503A0080" using ADDAR,

    "507E4000" using register 0x1F for SW_RESET . But  we could not resolve the issue. Please let us know if there is anything wrong with the sequence or the register values.

    Regards,

    Daman

  • 0 in reply to Daman Makhija
    TI__Mastermind 19780 points
    Hi Daman,

    The bit[7] should be cleared. It looks like you are setting it = 1. You should set register 0x31 = 0x0 if you are not using mirror mode. If you are using mirror mode, set register 0x31 = 0x1

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 140 points

    Hi Rob,

    Writting 0x0 to 0x31 register is also not solving the problem. Just now i tried this also. What next?, Any thing else i can try?

    One more observation regarding this phy is that when i configure this for 10Mbps by writing 0x0100 to register 0x0000 then it establish link with PC but when i configure it for 1Gbps by writing 0x0140 to register 0x0000 then link is not  getting established between this device and pc.

    Even though my application doesn't require 1Gbps speed but i am wondering whether these two problems are interrelated?

  • 0 in reply to Daman Makhija
    TI__Mastermind 19780 points
    Hi Daman,

    Forcing a 1G link is not supported by IEEE. So writing 0x0140 to register 0x0 should not result in a 1G link.

    Please try writing the value 0x1000 to register 0x31, and then restarting auto-negotiation, or soft reseting the PHY.

    If that does not work, then we need to start looking at what may be wrong with your PHY design.

    Step 1: Fix auto-mdix configuration of switch and DP83867. Ensure auto-mdix is not causing the problem.
    Step 2: Verify polarity of FLP for DP83867 is correct. Some switches don't have polarity auto-correction and this can cause a problem.
    Step 3: Measure the jitter of the reference clock provided to the DP83867. We are interested in the range from 1k to 10MHz.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 140 points

    Hi Rob ,

    Here are some observations -

    1. We tried writing the value 0x1000 to register 0x31, and then restarting auto-negotiation, or soft reseting the PHY.

    Link is not established .

    2.  Auto-mdix configuration of switch and DP83867 is fixed by writing 5008 to register 0x0010 .

    we verified that the polarity of FLP for DP83867 is correct

    We tried reading the status of register 0x0011 ,

    a. with PC - when link is established  , its showing the value 6C02 .

    b. with S/W - Link is not getting established , its showing the value 0002 .

    3.  We tried reading the status of Interrupt register also . 0x0013  ( After Setting all interrupts in reg. 0x0012 )

    With PC - Initially Bit 15 is set ( auto neg error int. )

    and after some time when link is established

    bit 12 is set ( page rec. int. )

    then bit 11 is also set ( auto neg comp int . )

    then bit 10 is also set ( link status chng int)

    With S/W  - all four bits ( 15 , 12 , 11 , 10 ) are zero . No interrupt is generated .

    4. We tried reading the status of  register . 0x0008 

    With PC - it is showing the value 6001.

    With S/W  - it is showing the value 0000.

    Regards ,

    Daman

  • 0 in reply to Daman Makhija
    Prodigy 140 points
    Hi Rob/ Anirudh
    As discussed I tried
    1) enabling autonegotiation by writing 0x1100 to register 0x0000, 0x5048 to register 0x0010, 0x0000 to register 0x0009 and 0x4000 to register 0x001f.
    2) forcing 100Mbps speed by writing 0x2100 to register 0x0000, 0x5028 to register 0x0010 and 0x4000 to register 0x001f.
    But still link is not established.

    Note : 1) In experiment 2 even though I am writing 0x5028 to register 0x0010 but after reading it's content is 0x5048, since bit 6& 5 is RO type as per data sheet.
    2) Content of register 0x006e is 0x006e and register 0x006f is 0x0020.
  • 0 in reply to Daman Makhija
    TI__Mastermind 18425 points

    Hello Daman,

    I was looking at the datasheet of the RJ-45 connector and noticed that the connector has provision to pull up the center taps of the transformer to VCC via pin 9. And from your schematics it looks like pin 9 is connected to 2.5V. For DP83867, the center taps should not be pulled to VCC. Can you try disconnecting pin 9 of RJ-45 connector from VCC?

    For enabling auto-negotiation:

    The default value of reg 0x00 is 0x1140 and reg 0x10 is 0x5048, leave those at that value.

    Write 0x0000 to register 0x09 to disable 1G advertisement. Read back this value to ensure it has been correctly programmed.

    Ready 0x04 to verify that it is 0x1E1.

    Write 0x4000 to 0x1F to initiate soft restart.

    For Forcing 100M speed:

    Write 0x2100 to 0x00 to force 100M, read back to confirm

    Write 0x5008 to 0x10 to force MDI, read back to confirm

    Write 0x400 to 0x1F to initiate soft reset

    Bit 6:5 are actually RW and can be programmed to enable disable Auto-MDIX. The RO in the datasheet is a typo. The fact that you do not see the value change even after writing to it might be due to some issue with the write operation. If register 0x6E is reading back 0x6E then it points to Speed Select[1:0] bits being 11 and PHY address being 0xE. This does not match the conditions in your schematics since there are not strap resistors being used. This might also be an issue with the write operation.

    I will recommend first disconnecting pin 9 of RJ-45 and seeing if that helps solve the problem. Then try to debug the write operation in your software.

    -Regards,

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Prodigy 140 points
    Lifting pin 9 worked.
    Thanks Anirudh & Rob for the support.