Other Parts Discussed in Thread: DS90UB960-Q1
Hello guys,
We will be using DS90UB960-Q1 or DS90UB964-Q1 deserializer in our current project and I'm trying to include the part into schematic design. There is a full datasheet of the DS90UB964-Q1 part (Link) which contains pretty good reference design (page 99). I would like to ask some questions that concerns schematic design though:
- Is it necessary to include some kind of ESD protection on the input part (where STP or coax cables will be connected) ?
- Can I connect FPGA I/O pin directly to PDB pin (with the RC network included) ?
- What is the logic level of GPIO pins? VDDIO ?
- We will use FPGA device to accept CSI-2 data from deserializer. I2C logic level on FPGA side is 1.2V. On deserializer side, it is 1.8V. Can you recommend me some I2C level shifter to translate from 1.2V to 1.8? I would like to benefit from 1Mbps I2C speed, of course. It would be great that I2C level shifter is automotive graded.
- There is no need for AC coupling capacitors on the output (CSI-2) side. We just need to keep those traces as short as possible (less than 2-3cm). Correct ?
- Can you recommend some ferrite beads for noise suppression (or at least to give me some kind of ferrite characteristics) ?
Thank you very much for your time and effort.
Sincerely,
Bojan.