Dear Sir,
I know 953/954 support two cameras inputs and combine them into one CSI2 stream. left-right or interlace.
I have some questions to be confirmed:
1: both of cameras are same, 1920*1080, 2 data lanes,720Mbps (360Mhz) mipi clock. I want to know , does 954 can support 4 date lanes while image sensor is with 2 date lanes? if yes, 954 clock is 720Mbps ,is it right?
2: I had seen some questions on pixel resolution and frame frequency for 953 and 954, it seems no any limit , but data throughput should be under the spec, e.g 4.16Gbs(26Mhz*160).
but I want to confirm:
if two image sensors works at sync mode , whatever the output format, left-right or interlace , it need internal line buffer for merging in 954 chip set, the size of line buffer is related with resolution, for example.
1920 *1080, raw 10, one line buffer size is 1920*10/8 = 2400 Bytes, maybe two line buffers are needed for merging operation.
so , is it no any limit for resolution for this scenario?
3. Also this scenario, a frame sync is from 954, there is about 600us jitters . my image sensors support external frame sync, but only one pulse is needed to trigger them, do not need continuous external sync wave(e.g. 30Hz or 60 Hz ), so no jitters between frames.
So, I want to know, is it okay if I just out one pulse to trigger these two sensors? can 954 merging operation work at this case( I don't know whether 954 internal merging logical need this sync edge or not)?
Best regards.
Ben
