PCA9555: Question on PCA5555 Interrupt Behavior

Hey Sam Pan91,

Is the PCA9555 something you are locked in with? Taking a quick look, there seems to be some errata associated with this device (INT function in particular). I would suggest the TCA9555 as this revision fixed the INT function abnormality.

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Going forward now, I will address the question you've presented assuming the TCA9555 is selected because the INT function is easier to predict.

Int data is stored originally with POR which should generate the read pulses for both ports; From this point the original conditions of the inputs are known. Afterwards, the INT registers only change during a read scenario (reading PORT0 will generate a read pulse for PORT0 but not PORT1). You can look at the functional diagram of this in the datasheet but referenced here as well.

You can see INT is triggered by an XOR gate which will only flag a 1 if one of it's inputs differs (00 and 11 result in zero whereas 10 or 01 result in 1 output). This effectively will place a voltage on the INT output's NFET which pulls low on the INT line. The XOR gate here references a D flip-flop which holds the last read value of the input. The other reference input is on the current state of the device. The D flip flop only changes its value when it receives a read pulse. Understanding this means we can move forward with "what if this occurs" scenario like you presented.

"1. PCA9555 detected GPIO#8 change and input port 1 register changed accordingly

2. PCA9555 assert INT to master

3. Master read input port 0

-INT will remain asserted here, the current inputs of this port also have been re clocked into the flip-flop

4. PCA9555 detected GPIO#0 change and input port 0 register changed accordingly

-The INT NFET sees a gate voltage from two sources now so both ports have triggered an INT condition

5. Master read input port 1
-One INT condition has been de-asserted but there is still another one; Note that the new input conditions are clocked into the D flip-flop for PORT1
6. Question – would PCA9555

a) Keep INT asserted forever due to master didn’t read input port 0 again
-My understanding of this device suggests INT will remain low until you re-read input port0
b) De-assert INT then assert INT again for the input port 0 register change"

-No, the device would remain low the entire time.

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I hope my explanation of this makes sense,

-Bobby