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DS90UB947-Q1: Pixel Speed/Position

Umberto Frangi
Expert 4045 points
Part Number: DS90UB947-Q1

Hi,

 I got some questions about this devices related to the pixel speed and position as follows: 

  • Can you confirm that in “Single-Pixel” mode  minimum frequency for pixel_clock is  25MHz and  in “Dual-Pixel” mode  is  50MHz, that is  equivalent to a minimum frequency of  25MHz on LVDS_PCLK (2 pixel per  clock period)? 

  • Is it possible to use “Dual-Pixel” mode if FPD-Link III interface  is set as SINGLE-LANE (the receiver has a single LANE)? 

  • We do not understand bits mapping  as reported  in Figure 15 and Figure 16 of  datasheet. If serializer generates stream video with mapping as in Figure 15, we have to set bit[7] of register 0x4F at ‘1’ (SPWG mapping) to have correct visualization. Otherwise with mapping as in Figure 16, bit[7] of register 0x4F should be at ‘0’ (OpenLDI mapping). The figures seems to be reversed.Can you verify?

    Thanks

Umberto