TMDS171: TMDS171

Hi Team,

I have chosen to use TMDS171I as a solution for TMDS buffer\retimer.

Enclosed the relevant part of my TMDS171 preliminary schematics.

I will much appreciate TI's review.

A few comments regarding the schematics:

1. The file does not include all schematics pages, in places where external connectivity is present I've described this connectivity as a PDF comment.  
2. Components that have the "NC" label near them (see below) will not be assemble on the PCB.TMDS171.docx

TMDS171_Design.pdf

In addition to the general review, appreciate TI's answer on a few questions related to the schematics:

1. In the component datasheet there is a "Sink Side Application" example, in which the TMDS171 DDC bus is connected to HDMI RX IC and have pull up resistors to 5V.

Will 3.3V pull ups work for SRC DDC (pins 46 & 47) and SNK DDC (pins 38 & 39)?

1. In the datasheet chapter 8.3.2 "Operating Timing" it says that "If OE is held low until VDD and VCC become stable there is no rail sequence requirement."

Does it means that as long as I hold OE low until both power sources are up, VDD & VCC can power up at any order with any time difference between the two,

and that td1 timing requirement (0-200us) can be violated?

1. What is the risk of using the TMDS171 as a DDC buffer i.e. connect the sink IC to DDC SNK and the HDMI connector to DDC SRC pins

So that the DDC bus will pass through the TMDS171?

Thanks,

Shlomi