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SN65DSI85: Timing Parameter

Nimesh Rana
Intellectual 470 points
Part Number: SN65DSI85

Hello,

We have board having HDMI to DSI Bridge chip from Toshiba for the HDMI data to MIPI DSI conversion and for the conversion MIPI DSI to LVDS we are using DSI to LVDS bridge chip SN65DSI85. At the output of D2L bridge chip, we are driving the 1080P resolution @ 60fps. Configuration is based on I2C using MSP430 controller. Currently, we are facing the flickering issueon LVDS panel.

The timing parameter of DSI out at H2D bridge chip and the display we are using are as below:

PCLK: 148.5MHz, HPW(44), HBP(148), HFP(88), and VPW(5),VBP(36),VFP(4)

Here is attached register settings used for the same. Can you please provide us the timing parameter used in generating those register settings for D2L?


Apart from above we please give your input for the below questions:

  1. What is the expectable jitter that D2L can handle?
  2. What will be the outcome if this jitter exceeds its limit?
  3. How many pixel jitters is allowed for total 1line, HPW+HBP, and HFP for the SN65DSI85?

Fullscreen D2L_register.txt Download 
9 1
a b
b 10
d 0
10 40
11 0
12 59
13 59
18 c
19 f
1a 0
1b 33
28 21
29 0
2a 21
2b 0
3c 0
3d 0
3e 0
18 c
20 80
21 7
22 80
23 7
24 38
25 4
26 38
27 4
2c 2c
2d 0
2e 2c
2f 0
30 5
31 0
32 5
33 0
34 94
35 94
36 24
37 24
38 58
39 58
3a 4
3b 4
d 1
9 1
a b
b 10
d 0
10 40
11 0
12 59
13 59
18 c
19 f
1a 0
1b 33
28 21
29 0
2a 21
2b 0
3c 0
3d 0
3e 0
18 c
20 80
21 7
22 80
23 7
24 38
25 4
26 38
27 4
2c 2c
2d 0
2e 2c
2f 0
30 5
31 0
32 5
33 0
34 94
35 94
36 24
37 24
38 58
39 58
3a 4
3b 4
d 1

Regards,

Nimesh Rana

  • 0
    TI__Mastermind 18655 points
    Hello Nimesh,
    As a starting point, you can use our DSI Tuner to generate a register configuration based on the input DSI format and the LVDS panel features.
    www.ti.com/.../DSI-TUNER

    I will confirm if the jitter details. We need to know the info below to figure out expected CLK jitter.
    -Input REFCLK
    -Expected LVDS CLK
    -Multiplier

    Regards
  • 0 in reply to Joel Jimenez0
    TI__Mastermind 18655 points
    Any update on the requested details?
  • 0 in reply to Joel Jimenez0
    Intellectual 470 points
    Hello Joel,

    We have successfully generated the test pattern from D2L without any flickering.
    Required data to figure out expected CLK jitter is as below:

    - Input REFCLK : 148.5MHz
    -Expected LVDS CLK : 132MHz to 148.5MHz
    -Multiplier - 3

    We need jitter values to confirm that the flickering we are observing on our display is not because of jitter.

    Regards,
    Nimesh Rana
  • 0 in reply to Nimesh Rana
    TI__Mastermind 18655 points
    Hello Nimesh Rana,

    Have you checked at the DSI line time? The line time (horizontal sync to the next horizontal sync timing from the APU) on the input is preserved when outputting onto the LVDS interface. If the line time is different from what is calculated by the tool, this will cause issues. Even if the DSI source is outputting streams in a burst manner, it is important for the DSI source to fill in the rest of the line time with blanking packets (or LP11) to meet the line time requirement.

    Please, export the .dsi file from DSI Tuner. I would like to check the timings from the output tab.

    Regards
  • 0 in reply to Joel Jimenez0
    Intellectual 470 points
    Hello Joel,
    Can you please let us know how to identify that our D2L bridge chip is working on burst, non-burst mode with Sync Pulse Mode or Sync Event Mode? Is there any register which indicates the mode of operating?
    Regards,
    Nimesh Rana
  • 0 in reply to Nimesh Rana
    TI__Mastermind 18655 points
    Hello Nimesh,

    No, there is not register you can use to know the input video mode. However, you can use the status register (0xE5) to know if an error is occurring in the DSI interface. Please, make sure you clear this field by writing (0xFF) before attempting to read the correct value.

    Regards