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HD3SS3220: Schematic Review

Part Number: HD3SS3220
Other Parts Discussed in Thread: 3220UFP-DGLEVM

I have a design with has a HD3SS3220. Is it possible that I could a my schematic reviewed by an Engineer ?

  • Hi Shmuel,

    Please send me your schematics to my e-mail:

    omar.moran@ti.com

    Thanks,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • Dear Luis Omar Moran,

    Thank you for the review.

    A couple of questions \ observations:-

    1. On VDD5 it appears from the check List that both a 1uF & 47uF is recommended but I didn't find the 47uF in the data sheet ?

    2. On VCC33 I didn't find any outline of the requirement for "100nF & 1uF capacitor array on pin 8 (VCC33) to GND"

    3. We are implementing a UFP thus as far as I understand the following pins (open collector) can be left floating with no pull up : ID, VCONN_FAULT_N, CURRENT_MODE & INT_N/OUT3(audio accessory connection detection not required) ?

    Best regards

    Shmuel
  • Hi Shmuel,

    1. These caps are recommended for TI, even in the EVM of the HD3SS3220 a 47uF cap is placed since is needed for VCONN (Bulk cap between 10uF and 220uF).
    2. Evenly, in VCC33 is recommended to place caps of 1uF & 100nF. We could share the schematics for our EVM to provide a guidance.
    3. For UFP application you could leave them floating.
    Regards,
    Luis
  • Dear Luis,

    Thank you for your replies and help once again.

    1. Since I am implementing a UFP then isn't the VCONN feature irrelevant ? This is why I left pin 24 unconnected ? If so is the additional 47uF still relevant ? If yes - what is it needed for ?
    2. You sent me the 3220UFP-DGLEVM INT027: TUSB3220 schematic and I used this to help me with the design. It appears from the schematic that only a 0.1uF is implemented on the VCC33(pin 8) I could not find the 1uF. In fact there is a "FB1 220@100MHz" between 3P3V and the 3P3V_VCC which I did not implement - should I be placing this (I assume it is some sort of ferrite bead ?). Is the VCC33 so sensitive or is this something that is isolated for the EVM design ? If yes do you have a P/N for it ? I see that on the 3P3V supply there is a 10uF on the output of the TPS62082DSGT but I have this also on my implementation of my regulator (+5V to +3.3V) which I did not send you ! I assume that the 1uF does not relate to this 10uF ?

    Bets regards

    Shmuel
  • Hi Shmuel,

    1. For UFP application is not relevant. Hence, this bulk cap of 47uF in VDD5 can be omitted.
    2. For VCC33 the recommendation is to place 1uF and 100nF caps to avoid enter noise into the device, this assessment is from designers. In the EVM are placed a ferrite bead and 100nF to protect the device of noising since this power signal is sensitive. Hence, for most of applications our recommendation is place 1uF and 100nF. Even, only the 100nF is "mandatory" if your design has a low noise coupling.

    Thanks,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • Dear Luis,

    So I will removed the 47uF from the VDD5 and keep the 0.1uF and 1uf on the VCC33.

    Since our +3.3V is quite stable (we are using a EP53F8QI powered by VBUS) thus is it safe to assume that I will not need the ferrite bead that is on the EVM ?

    Thanks

    Shmuel
  • Hi Shmuel,

    Your scenario is feasible, hence please keep the configuration you have mentioned above.

    Regards,
    Luis