DP83867IS: What is difference for CLK_O_SEL setting

Hello Geet-san,

>You can use Channel A and B which are enabled for any data rates.

Understood about above.

I understood why TI prepare bitfield for each channel is for 10Base/100Base communication.

In case of 10Base/100Base, there are TX port and RX port separately. And also, port is used only one each other. So user can choose one of following port to input/output data.

01011: Channel D transmit clock
01010: Channel C transmit clock
01001: Channel B transmit clock
01000: Channel A transmit clock

Therefore, when user will use 10Base or 100Base, user need to take care this setting, but case of 1000Base, we can choose any of above.

Best Regards,

Hello Geet-san,

Thank you for your reply.

Let me confirm about below just in case.

* I believe "transmit clock" and "receive clock" which are descrived in CLK_O_SEL bitfield mean "GTX_CLK" and "RX_CLK".

  Is my understanding correct ?

BR,

Hi Ryuuichi,

The transmit clock you are referring to in register 0x170 is in regards to the line driver clock. This is not the GTX_CLK or GRX_CLK.
When operating in 1Gbps, channel A/B/C/D operate in physical full-duplex, where they transmit and receive data over the same pair.
This output clock option just allows you to monitor the clock accuracy of the clock recovery within the PHY.

Those bits concern the MDI (cable interface) and not the xMII (MAC facing pins). What exactly would you like to do?
Applications do not require the use register 0x170.

Hello Ross-san,

THank you for your reply.

>The transmit clock you are referring to in register 0x170 is in regards to the line driver clock. This is not the GTX_CLK or GRX_CLK.
>When operating in 1Gbps, channel A/B/C/D operate in physical full-duplex, where they transmit and receive data over the same pair.
>This output clock option just allows you to monitor the clock accuracy of the clock recovery within the PHY.

From above, I understand as shown below.

* clock from "CLKOUT" pin is used clock which is recovered from CDR.

If above is correct, when they set receive clock for CLKOUT, I think that clock from CLKOUT and "RX_CLK" are same.

Because, RX_CLK is recovered clock from CDR. So, I could not understand why you said that  "This is not the GTX_CLK or GRX_CLK."

If my understanding, could you please correct me ?

>Those bits concern the MDI (cable interface) and not the xMII (MAC facing pins). What exactly would you like to do?

Yes, Understood.

I heard customer just want to use this clock(CLKOUT) for source clock of SOC, not for PHY itself.

Thanks in advance,

Hi Ross-san,

Thank you for your reply.

I could image almost.

I understood that CLKOUT comes from clock of MDI parts.

In case of RX, clock from CLKOUT comes from clock after performing CDR.

And in case of TX, clock from CLKOUT comes from clock before perforing CDR.

Both clock come from PMA block directly.

Is my understanding almost correct ?

Best Regards,