Other Parts Discussed in Thread: DS92LX1621
We are attempting to use a DS90UB902Q deserializer in some test hardware receiving data from the DS92LX1621 part. It is an imaging/camera application with the DS90UB902Q receiving image data from a remote DS92LX1621 and I2C communication occurring through the parts with the DS90UB902Q configured as a slave and the DS92LX1621 as a master. We are having difficulties reliably achieving LOCK of the two parts on power up. What we have observed, however, is the LOCK is reliably established when the deserializer is switched from SLAVE to MASTER mode. This is while no I2C transactions are actually occurring (no changes to I2C registers taking place anywhere in the system).
Anyone have any ideas why this is occurring? We are hoping it's explanation might be a clue to our difficulty of achieving LOCK while in the needed SLAVE/MASTER configuration.