TLK6201EA: Output CML Interface to FPGA LVDS Input

Mark Heh

Part Number: TLK6201EA

The outputs are CML type with "On-chip 50-Ω back-terminated to VCC. " What does it mean for it to be "back-terminated" to VCC? Does it simply mean that they are both pulled up to VCC?

What is the recommended output structure to interface the output of the TLK6201EA with a LVDS configured input of a Xilinx FPGA? Figure 18 and 19 of SCAA059c recommends different methods, but I've also seen other methods.

over 7 years ago

0 Luis Omar Moran over 7 years ago

TI__Genius 16150 points

Hi Mark,

DOUT+/- are internally pulled-up through a 50ohm resistor. Please take a look into this application note to interface between LVCPECL, VML, CML and LVDS levels:
www.ti.com/.../slla120.pdf

Best Regards,
Luis Omar Moran
High Speed Interface
SWAT Team

0 Mark Heh over 7 years ago in reply to Luis Omar Moran

Intellectual 270 points

Hi Luis,

Below are some different ways of terminating based on different TI literature. The document you pointed me to has a different scheme that the one in SCAA059C. See below.

http://www.ti.com/lit/an/scaa059c/scaa059c.pdf

www.ti.com/.../slla120.pdf

Thanks,

Mark

0 Lee Sledjeski over 7 years ago

TI__Mastermind 43795 points

Hi Mark,

There are some important variables in how to connect this interface together. If the data is encoded and DC balanced, the recommended solution would be to simply AC couple the link and allow the internal 100 Ohm LVDS termination on the FPGA to provide the impedance match.

If the data is not encoded with 8b10b or similar, please provide as much information as possible about the interface since a DC coupled solution will likely be needed.

Thanks and Regards,

Lee

Interface

Interface forum

TLK6201EA: Output CML Interface to FPGA LVDS Input