Hi,
For a new project, i want to use a TLK10232 for 10Gb link.
I want to know if it's possible to use this component only with these default register?
The high speed side need to comunicate at 10.312Gb and Low speed at 3.125Gb.
In my schematic :
1/ MODE_SEL = ST = '0' (pull down 4.7K) for 10GBASE-KR mode.
2/ Refclk0 = refclk1 = 156.25MHz (refclk1 is only present in case of future problem but only refclk0 will be used).
3/ All channel A&B will be used at the same frame rate HS & LS side.
In datasheet, we cans see that :
1/ default mode = 10GBASE-KR (SW_PCS_SEL = '1')
2/ default HS & LS serdes clock = REFCLK0 (REFCLK_SW_SEL = LS_REFCLK_SEL = '0')
3/ default pll multiplier for LS side = x10 (LS_PLL_MULTIPLIER[3:0] = "0101");
So my problem is for HS PLL MULTIPLIER.
Default setting is x20 (HS_PLL_MULTIPLIER[3:0] = "1101).
At 10.312Gb in HS side, i need a multiplier of 16.5 (HS_PLL_MULTIPLIER[3:0] = "1100").
It will be say that the default setting is a HS SPEED SIDE of 12,5Gb (not frequency possible) for a 156.25MHz refclk input.
Problem is that i cannot use Refclk1 at a frequency of 128.9MHz in order to produce a 10.312Gb in HS side because, by default, HS & LS serdes clock = refclko.(same clock).
Is this register is really at x20 by default or it's a mistake?
it's seem to be more coherent that this register is x16 by default. In this case the HS and LS side work in a coherent configuration.
And is it possible to find a configuration where no register modification is necessary?
My design is not in production yet, so I can do some modification if necessary.
Thanks
Best Regards.
