Part Number: TPS65986
Team, we are still trying to clarify the High/Low Region size, and locations. It still seems like like the max size of the 'ID, Header, & configuration data' + 'application code' sections is 64kB, and not 68kB like figure 3-4 shows in the FW Update App-Note.
I say this because using FLrr, I get:
FLrr Region 0 = 0x0000_2000
FLrr Region 1 = 0x0001_2000
So, that is only 64kB between each of these regions. This is especially confusing when the FW upgrade steps ask you to run the FLem command to erase X number of 4kB blocks from the FLrr region address. In the sample code, it erases 17 4-kB blocks (so 68kB). If I do FLem starting at 0x0000_2000 using 17 4-kB blocks, I'd erase up to 0x0001_3000, which is supposedly past the start of region 1.
Why is the sample code / TI documentation saying the 'ID, Header, & configuration data' + 'application code' sections is 68kB, but based on FLrr, it is 64kB? When I do a FLem command, should I be erasing 16 or 17 blocks?
Based on other response, it looks like the latest config tool can place High Region as low as 0x0001_2000, but is this a limitation of the config tool right now (apparently limiting application code to 60kB, to stay within 64kB max for Header + App Code)... or is the FW Update documentation incorrect, and the size limit truly is 64kB for Region Header + App Code?