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TUSB9261DEMO: The "Security Erase Prepare" and ""Security Erase Unit" commands have no effect.

Amy Liu
Intellectual 260 points
Part Number: TUSB9261DEMO
Other Parts Discussed in Thread: PMP

Hello,

I sent these two ATA commands to the storage device successfully, first the "Security Erase Prepare", then the "Security Erase Unit", but the storage device was not erased. What could be the problem?

Thanks,

Amy

  • 0
    TI__Genius 11255 points
    Hello Amy,

    We are taking a look at your request. We'll send our comments shortly.

    Regards,
    Roberto
  • 0 in reply to Roberto Diaz
    Intellectual 260 points
    I sent the two commands, but not 100% sure that they were successful. Trying to set things up so that I can see debugging messages. Can you please provide code samples showing how you will send these two commands and verify it works in your setup? The firmware version is TUSB926x_FW_v1.05.
  • 0 in reply to Amy Liu
    Intellectual 260 points

    More debugging shows that "Security Erase Prepare" command was sent and completed successfully. But after sending the "Security Erase Unit" command, the ahci_wait_complete() returns STATUS_TIMEOUT even if the timeout is set to 60 seconds. The command was set up like this:
     
    // set up buffer
    ti_memset(&ata_cmd, 0, sizeof(ata_cmd));
    ti_memset((void*)datapath_ram->wrap_window_memory_placeholder, 0, 512);
    ti_memset((void*)datapath_ram->wrap_window_memory_placeholder, 0x01, 1);

    // populate ata command
    ata_cmd.fis.FIS_type = H2D_REGISTER_FIS_TYPE;
    ata_cmd.fis.CRRR_PMP = 0x80;
    ata_cmd.fis.command = ATA_SECURITY_ERASE_UNIT;
    ata_cmd.bIsWriteCmd = TRUE;
    ata_cmd.bUseMemoryWrapWindow = TRUE;
    ata_cmd.dDataByteCnt = 0x200;

    // send command and wait complete, but never completes
     
    Anything wrong with this command setup? And what might cause the command never to complete? For the "Security Erase Prepare" command, should I disable/enable D2H Register port interrupt or "PIO Setup port interrupt"?

    Thanks,
    Amy

  • 0 in reply to Amy Liu
    TI__Expert 4325 points

    Hi Amy,

    We cannot provide much support on custom FW and we've never tested these specific commands.  The only guidance I can give is that

    bUseMemoryWrapWindow should be FALSE;

    D2H and PIO interrupts should be enabled already.  If you must send multiple ATA commands for a single SCSI command, then you need to disable the D2H interrupt enable and wait for complete.  Then re-enabled the interrupt before issuing the last command.   Reference scsi_handle_start_stop_unit() for an example.

    Regards,

    Brian

  • 0 in reply to Brian Quach
    Intellectual 260 points
    Hi Brian,

    Thanks so much for your suggestion! Can you please clarify a couple things?

    1. "Security Erase Unit" command has 512 byte data load. Is it correct to put the data in the datapath_ram->wrap_window_memory_placeholder? If it is correct, shouldn't bUseMemoryWrapWindow be TRUE?

    2. I need to send two commands "Security Erase Prepare" and "Security Erase Unit" to complete a Security Erase. "Security Erase Unit" uses PIO data-out protocol. Should I disable "PIO Setup port Interrupt" before sending this command? I am confused about when I should use D2H_REGISTER_FIS_INTR and when I should use PIO_SETUP_FIS_INTR...

    Thanks!
    Amy
  • 0 in reply to Amy Liu
    TI__Expert 4325 points
    1) Yes, still put the data there but set to FALSE.
    2) Since Security Erase Unit is the second command, you should re-enable INTR before issuing that command. Follow the example I referenced.

    Regards,
    Brian
  • 0 in reply to Brian Quach
    Intellectual 260 points
    Thanks, Brian!

    Can you please confirm which interrupt I should touch here, PIO_SETUP_FIS_INTR or D2H_REGISTER_FIS_INTR? "Security Erase Prepare" has no data load, while "Security Erase Unit" has.

    Thanks so much!
    Amy
  • 0 in reply to Amy Liu
    TI__Expert 4325 points

    Hi Amy,

    Disable D2H before sending non-data command Erase Prepare.  Then re-enable after it is completed.  Leave enabled for Erase Unit.

    Regards,

    Brian 

  • 0 in reply to Brian Quach
    Intellectual 260 points

    Hi Brian,

    I was able to collect some debug messages after sending the two erase commands:


    [0000039296] -> ahci_build_cmd() - cmd_slot = 0.
    [0000039296] -> ahci_issue_cmd() - P0, cmd_slot = 0, queued_cmd = 0.
    [0000039297] AHCI P0IS = 0x00000001, IE = 0x7900005f.
    [0000039297] -> ahci_handle_d2h_reg_fis()
    [0000039297] PRD byte_cnt = 0.
    [0000039324] -> ahci_register_ata_callbacks() - 0x08008985, 0x0800892f, 0x00000000.
    [0000039324] -> ahci_register_port_init_complete_callback() - 0x08008431.
    [0000039325] -> ahci_register_ata_callbacks() - 0x08008985, 0x0800892f, 0x00000000.
    [0000039325] -> ahci_register_port_init_complete_callback() - 0x08008431.
    [0000039500] -> ahci_build_cmd() - cmd_slot = 0.
    [0000039500] -> ahci_issue_cmd() - P0, cmd_slot = 0, queued_cmd = 0.
    [0000039501] -> ahci_wait_complete() - 9999 ms remaining waiting for addr[0xfb000138] = 0x00000000.
    [0000039501] Security Erase Prepare sent successfully!
    [0000039501] -> ahci_build_cmd() - cmd_slot = 0.
    [0000039501] -> ahci_issue_cmd() - P0, cmd_slot = 0, queued_cmd = 0.
    [0000039501] AHCI P0IS = 0x40000000, IE = 0x7900005f.
    [0000039501] -> ahci_get_TFD_info() - P0TFD = 0x451.
    [0000039501] AHCI task file error! P0TFD error = 0x04, status = 0x51.
    [0000039501] -> ahci_get_TFD_info() - P0TFD = 0x451.
    [0000039501] -> ahci_fatal_error_recovery()
    [0000039501] -> ahci_stop()
    [0000039501] -> ahci_wait_complete() - 2000 ms remaining waiting for addr[0xfb000118] = 0x00000000.
    [0000039501] -> ahci_start()
    [0000039502] -> ahci_wait_complete() - 9999 ms remaining waiting for addr[0xfb000138] = 0x00000000.
    [0000039502] Security Erase Unit was sent successfully!


    It looks AHCI got Task File error. Is P0TFD updated by SSD? Do you know what value 0x451 means?

    Thanks,
    Amy

  • 0 in reply to Amy Liu
    TI__Expert 4325 points
    Hi Amy,
    The SATA registers follow the SATA spec so you can find the definitions in the SATA and AHCI specs.
    Regards,
    Brian