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DS125DF1610: CrossPoint Switch Status and Control

Part Number: DS125DF1610

Hello,

I'm configuring the crosspoint switch in the DS125DF1610 and am somewhat confused with the Signal Detect status when forcing an SD through the Output Channel Number. 

I have configured the crosspoint switch as follows:

Input          Output         XPNT_EN, EQ_BUFF_EN(1:0),EQ_DATA_MUX_IN(1:0)      EQ_CTRL_MUX_IN(1:0)

A       --->       0              0x96(4:0) = 0x1C                                                                        0x9B(1:0) = 'b00

C       --->       1              0x96(4:0) = 0x1E                                                                        0x9B(1:0) = 'b10

D       --->       2              0x96(4:0) = 0x1F                                                                        0x9B(1:0) = 'b11

B       --->       3              0x96(4:0) = 0x1D                                                                        0x9B(1:0) = 'b01

When I force a Signal Detect on Channel 3 by setting bit 7 in Channel 3 Register 0x14, I see the SD status bit on Channel Input D get set, not Channel B as expected.  Other Cross connected channels behave similarly.  This is counter-intuitive to the statement in section 7.3.4 Cross Point Switch.  Under #2 it states:

2. Control bus mux – Selects where the signal detect and EQ control bus should be connected. This setting
should mirror the data path mux setting. Note, when an EQ is connected to another channel’s CDR the EQ
becomes associated with that CDR’s register set. For example, if the cross point was configured to do point
to point switching from the inputs of channel 0 to the output of channel 1 and the inputs of channel 1 to the
outputs of channel 0, the EQ physically located at the pins for inputs of channel 0 would be accessible
through the register set of channel 1.

Though the statement only mentions control, I would expect the status to follow as well.  Is there a configuration setting that I'm missing to get the input channel status from the output channel number?

  • Hi John. I double checked with our digital design team. Let's say you have channels 0 and 1 within the same cross-point quad, and cross-point lane swapping was respectively implemented via channel registers 0x96 and 0x9B and for these two channels. Then, if you select the channel registers for channel 1, if you were to set 0x14[7]=1 by design we expect that the signal detect block located in channel 0 would be forced enabled.

    Cordially,

    Rodrigo Natal]

    HSSC Applications Engineer

  • This is what I am seeing:

    Using your example, I force a signal detect through channel 1's control registers but I must read channel 0's registers to see Signal Detect status being set. I understand why this happens, just confused by the paragraph in the datasheet and why one wouldn't connect the status from the input side to the register set from which the channel is being controlled.

    Can you clarify channel register offsets 0x02(7:0) MULTI_PURP_STATUS and 0x0C(7:4) STATUS_CONTROL? The Description of these bits is a bit cryptic. I was hoping these were the controls for re-routing status from channels on the other side of the cross connect.
  • Hi John.

    Using your example, I force a signal detect through channel 1's control registers but I must read channel 0's registers to see Signal Detect status being set

    This doesn't make full sense to me. If you write 0x14[7]=1 on channel 1 registers, then you should be able to read that '1' value you wrote. Channel register 0x78[5] is the signal detect status observation point. If you set 0x14[7]=1 on channel 1 registers then I would expect that you would see that 0x78[5]=1 on channel 1.

    Channel register 0x02 is the retimer status register. For the default setting of 0x0C this register allows you to observe the status signals listed below for a given channel. Channel register 0x02 would not allow you to observe signal detect from other channels. 

    CDR Status [7:0]

    Bit[7] = PPM Count met

    Bit[6] = Auto Adapt Complete

    Bit[5] = Fail Lock Check

    Bit[4] = Lock

    Bit[3] = CDR Lock

    Bit[2] = Single Bit Limit Reached

    Bit[1] = Comp LPF High

    Bit[0] = Comp LPF Low

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Hi Rodrigo,
    This doesn't make full sense to me either. If I write 0x14[7]=1 on channel 1 registers, then I can read that '1' value I wrote. But when I read 0x78 for channel 1 I get 0x00 not the 0x20 I expect if I just forced a Signal Detect on channel 1. But I do see 0x20 in register 0x78 in channel 0. Thus the reason for this thread...

    The Devices we are using have the following marking on them 55ZCRQ9G1. Are there any Errata on this device?
  • I've confirmed with the team that this signal detect channel register status bit behavior with cross-point lane swapping is expected. Sorry for the confusion.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Thanks Rodrigo... I was afraid you were going to say that...
  • Hi Rodrigo,
    One last question, are there other status that behave this way that I should be aware of? Or anything that is related to the EQ.
  • Not that I'm aware of. CTLE, DFE, and HEO and VEO channel register values should all map out as expected when implementing cross-point lane swapping.