DP83822IF: FLP output after reset release(L->H)

Hirotaka Matsumoto

Part Number: DP83822IF

Hi all

Would you mind if we ask DP83822IF?
On the our customer's board, our customer could not get the FLP signal in Oscilloscope.

<Contents>
1. power up
2. After 150ms, reset release(L->H)
3. They could not get the FLP signal in Oscilloscope

And then,
1. MAC I/F : RMII, slave configuration
2. Clock : 50MHz±50ppm
3. RBIAS voltage : 1.0V
-> We think that it doesn't matter about hardware.

<Question1>
In spite of Hardware Bootstrap Configurations, we thinks after reset reset release(L->H), FLP outputs.
Our customer's Hardware Bootstrap Configurations are all default.
Does it requre EEE_EN=1 for FLP?
Is our recognition correct?

<Question2>
Does FLP output after power-up 1.5s?

If you have some advice, could you let us know?

Kind regards,

Hirotaka Matsumoto

over 7 years ago

0 Rob Rodrigues over 7 years ago

TI__Mastermind 19780 points

Hi Hirotaka,

Could you please provide a schematic of the customer's design?

FLP is output from the PHY when the bootstrapping has at least the following settings:

FX_EN = 0

RMII_EN = 1

XI_50 = 1

AN_EN = 1

If AMDIX_EN = 1 then FLP will come out of RD and TD pins, alternating between the two.

This all depends on the PWDN_N pin being pulled HIGH as well.

Yes FLP should start coming out of the PHY after power-up as shown in "Timing Requirements, Power-Up Timing" section of datasheet. 1.5s

I would also ensure your LEDs are pulled high or low during power-up. Place an external resistor. If the LED pins float to an intermediate voltage during power-up, it can cause the PHY to not initialize properly.

Best Regards,

0 Hirotaka Matsumoto over 7 years ago in reply to Rob Rodrigues

Guru 27585 points

Rob san

Thank you for your reply.
We sent customer's design using private message.

Kind regards,

Hirotaka Matsumoto

0 Hirotaka Matsumoto over 7 years ago in reply to Hirotaka Matsumoto

Guru 27585 points

Hi team

Furthemore, when our customer sets EEE_EN=1 using hardware strap setting(RX_D1 Mode=2), FLP(62.5us pulse) started coming out of the PHY after reset(1.4s～1.5s).
Does it require EEE_EN=1 setting?

And then, strap configuration were determined after T3(Hardware configuration latch-in time for power-up) from reset or power up
Is it correct?

Kind regards,

Hirotaka Matsumoto

0 Rob Rodrigues over 7 years ago in reply to Hirotaka Matsumoto

TI__Mastermind 19780 points

Hi Hirotaka-san,

EEE_EN should not impact FLP coming out of the PHY after reset.

Yes, the voltage is sampled at the pin, and straps are configured from that voltage, at time T3 in the datasheet Reset Timing and Power-Up Timing tables.

Best Regards,

0 Hirotaka Matsumoto over 7 years ago in reply to Rob Rodrigues

Guru 27585 points

Rob san

Thank you so much for your reply.

Just in case, we sent you customer's design using private message.
We think that there is no problem for FLP burst.
If you have some advice, could you let us know?

Kind regards,

Hirotaka Matsumoto

0 Rob Rodrigues over 7 years ago in reply to Hirotaka Matsumoto

TI__Mastermind 19780 points

Hi Hirotaka-san,

I have answered you in private message. I will close this thread now.

Best Regards,

0 Hirotaka Matsumoto over 7 years ago in reply to Rob Rodrigues

Guru 27585 points

Rob san

Thank you so much for your reply!

Just now, the customer problem was solved.
They had some mistake.

Kind regards,

Hirotaka Matsumoto

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DP83822IF: FLP output after reset release(L->H)