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TL16C752C: TL16C752C IOR/IOW Timing

Macs
Expert 3910 points
Part Number: TL16C752C

Hello Team;

I have question for IOW/IOR timing with CS signal to access.

Reference to Figure 1.General Write Timing on page 11(or Figure 2. General Read timing on page 12) of datasheet,
IOR should be low  while /CS=Low, Or, /CS  should be low while IOR=Low, to access data.(

However, does it be possible following case?

1) /CS=Low first, then IOW=Low for more than t13w+t6h period,
     then /CS=High and then IOW=High followed

 2) opposite timing: IOW=Low first, then /CS=Low for more than t13w+t6h period,
     then IOW=High and then /CS=High followed.

Could you tell me above case possible to access data ?

Thanks

  • 0
    TI__Guru 72981 points
    Hey Macs,

    I have not personally had the chance to mess with the write/read timing of the UART devices however my understanding is:

    "1) /CS=Low first, then IOW=Low for more than t13w+t6h period,
    then /CS=High and then IOW=High followed "

    t6h signifies when either CS or IOW changes from Vcc/2 until the time the address begins to change. If you are changing the address before CS/IOW changes before both signals go high then I suspect you may run into issues/unexpected problems when writing. However, if the address is not being changed then it does not matter which signal goes high first.

    This applies to your second condition as well.

    "Could you tell me above case possible to access data ?"
    To reiterate, I believe you may see issues if the address is changing before BOTH IOW/CS go high but I do not suspect any problems to occur if either signal goes high first before the address changes.

    Thanks,
    -Bobby