DP83867CR: MAC and PHY clock for low latency

Tomas Correa

Part Number: DP83867CR

Dear All,

in the document "Latency in Factory Automation" (snla240) it is written that the user can configure RGMII_TX_HALF_FULL_THR to 0x1 when MAC and PHY share the same clock. It is not completely clear for me which clocks must be the same, because we have at least 3 clocks in the system: RX_CLK (recovered from the network), TX_GTX (supplied by the MAC in the RGZ device) and the PHY local clock at XI pin.

Therefore, my question is: which clocks need to be the same for being able to reduce RGMII_TX_HALF_FULL_THR?

KR,

Tomas

over 7 years ago

0 Rob Rodrigues over 7 years ago

TI__Mastermind 19780 points

Hi Tomas,

If TX_CLK(generated by the MAC) is synchronous with the system reference clock of the PHY(XI pin), then the RGMII_TX_HALF_FULL_THR can be set to 0x1 to eliminate variation there.

Best Regards,

0 Tomas Correa over 7 years ago in reply to Rob Rodrigues

Prodigy 80 points

Hi, Rob,

thanks for the answer. I was imagining that... This means that the PHY uses the XI clock as reference for sending packets, right? How is then possible to use synchronous Ethernet?

Cheers,

Tomas

0 Rob Rodrigues over 7 years ago in reply to Tomas Correa

TI__Mastermind 19780 points

Hi Tomas,

The PHY does not always use the XI clock as reference for transmitting packets on the wire. The recovered receive clock, in 1000BASE-T mode is used when the PHY is slave. In that case there is a FIFO between the digital and analog blocks that bridges the two different clock domains.

Best Regards,

0 Tomas Correa over 7 years ago in reply to Rob Rodrigues

Prodigy 80 points

Hi, Rob,

Can I only implement synchronous ethernet with this PHY in 1000BASE-T? How is it possible? I would guess that if a connect several nodes, each node with two ethernet ports, in dasy-chain, I would need to use the clk_out pin of the PHY at port 0 to drive the XI of the PHY at port 1. Am I correct?

KR,

Tomas

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DP83867CR: MAC and PHY clock for low latency