DS90UH926Q-Q1: Output Data Valid Times

F.N

Part Number: DS90UH926Q-Q1

Hi team,

My customer thinks it is very hard to understand DS90UH926Q-Q1 datasheet Figure 6 Output Data Valid Times.
The customer asks whether the figure (A) or (B) below is correct.

I think (A) is correct. Because there is following descrition in the datasheet page.11 table.

tROS | Data Valid before PCLK – Setup Time

tROH | Data Valid after PCLK – Hold Time

However, if (A) is correct I can not understand why data valid time is so narrow and not related to PCLK frequency.

Please let me know the answer.

Best regards,
Fumio Nakano

over 7 years ago

0 Palaniappan Manickam over 7 years ago

TI__Genius 10475 points

Hello,
Your understanding is correct, A is the correct answer. Keep in mind the tROS and tROH are min specs in the datasheet table.

0 F.N over 7 years ago in reply to Palaniappan Manickam

TI__Expert 8760 points

Hello Palaniappan-san,

Thank you for your prompt reply.

The customer wants to know the outputs propation delay spec. Because the customer uses DS90UH926Q-Q1
with lower PCLK frequency than 85MHz and needs more wider valid range.

Is it possible to convert the setup / hold spec into propation delay spec and present it?

Best regards,
Fumio Nakano

0 Palaniappan Manickam over 7 years ago in reply to F.N

TI__Genius 10475 points

This is a min spec in the datasheet and spec'ed for the worst-case condition (highest PCLK 85 MHz), so atleast 2.2ns for setup and 3ns for hold irrespective of PCLK.
Lower PCLK frequency means bigger UI so that means more margin to meet the setup and hold.

0 F.N over 7 years ago in reply to Palaniappan Manickam

TI__Expert 8760 points

Hello Palaniappan-san,

Thank you for your reply.

I estimated DS90UH926Q-Q1 output propagation delay as follows.

Is this correct? Please let me know.

Best regards,
Fumio Nakano

0 Palaniappan Manickam over 7 years ago in reply to F.N

TI__Genius 10475 points

Hello,
Sorry for the delay in response. I am not sure what your definition of tROPD is, but irrespective of the PCLK duty cycle the min tROS and tROH values remain the same as they are referenced to the PCLK rising edge.

Interface

Interface forum

DS90UH926Q-Q1: Output Data Valid Times