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SN65DP159: Input skew tolerance

Kawai
Guru 19785 points
Part Number: SN65DP159

Hi Team,

It might be a general question, however, could you please tell me about the input skew tolerance for DP159 ?

Input inter-pair skew tolerance between lanes are 1.8ns (MAX) and this is only applied to the data lanes (D0, D1, D2).

My question is, how should we think of the skew or phase relation between data and clock lane ?

I am wondering how DP159 can correctly sample the data without the spec of the phase relation.

Best Regards,

Kawai 

  • 0
    TI__Guru 60870 points
    Hi Kawai,

    The skew tolerances in the DP159 datasheet are influenced by the HDMI specification. There is no inter-pair skew specification for the clock lane in the specification. The TMDS data lanes transmit data at a rate of 10 bits per TMDS clock period (HDMI 1.4b) or 40 bits per TMDS clock period(HDMI 2.0), the clock is used by the receiver as a frequency reference for data recovery on the data channels.

    Regards,
    JMMN
  • 0 in reply to JMMN
    Guru 19785 points

    Hi JMMN-san,

    I understand the HDMI specification that it does not have inter-pair specification between clock lane and data lane.

    However, my question was that DP159 can always handle the input signal ignoring the skew between the data and clock lane or not.

    I think the device has a PLL first locks to the input clock then somehow builds the sampling clock which is 90 degrees phase shifted.

    Is my recognition correct ?

    Best Regards,
    Kawai