DS125DF1610: DS125df1610

Hi again Rodrigo,

To make this clear to me:
Case 1: 0 and 2 are swapped with each other and 1 and 3 are swapped with each other. Channels that are routed through the switch to its partner, the observation point for the Signal Detect is the Output Channel.
Input Output
2 --> 0 Signal Detect shows up on Channel 0
3 --> 1 Signal Detect shows up on Channel 1
0 --> 2 Signal Detect shows up on Channel 2
1 --> 3 Signal Detect shows up on Channel 3

Case 2: Channels that are completely scrambled, the observation point for the Signal Detect is the Input Channel
Input Output
3 --> 0 Signal Detect shows up on Channel 3
2 --> 1 Signal Detect shows up on Channel 2
0 --> 2 Signal Detect shows up on Channel 0
1 --> 3 Signal Detect shows up on Channel 1

In other words, Signal Detect Status follows the switch settings only if the channels are swapped with each other.

-Jack Wallace

Ok Rodrigo,

Is there anyplace I can go to find an errata on this device?

I may have mentioned in a previous post that we are using 20 of these things in our design.  We have 10 Tx and 10 Rx CDRs.  We have been working on the SW driver for this device for over three weeks trying to nail down the cross point switch settings and the frustration level is reaching a critical point.  We have been seeing anomalous behavior from this thing in addition to the Xpnt settings mentioned In CASE 1 and 2 above.  The behavior is typical of xpnt switches that have channels completely scrambled.  I have listed 5 ports that exhibit this behavior and these are not the only ones.  These were included to show that it isn't an isolated device nor a single Quad within the device.   

For Port 4 below, we force a signal detect on Channel 7, but see the SD status bit set in Channel 6's Register set.  How is this possible?  Does the signal detect control follow the path of blue arrows through channel 4 or does it traverse through Channel 5, from input side of Channel 7?  An alternate possibility is that we are not setting the cross point up in a specific order that is undocumented.  However if this were the case I suspect that none of our settings would work.  You may note that this happens to all channels within the Quad.

-Jack

Hi John. I will take the action to reproduce your settings in my lab using a DS125DF1610EVM. Pending results, I will get back to you with my recommended registers configuration as well as expected retime behavior for these settings.

Would you be able to provide me your work email address? I'd like to communicate directly on this item given the urgency.

Cordially,

Rodrigo Natal

HSSC Applications Engineer