DS90UB964-Q1: Should I need to consider blanking time for CSI-2 throughput?

kenshow

Part Number: DS90UB964-Q1

I have an additional question about the blow posted:

e2e.ti.com/.../2300242

This case is following:

sensnor output: resolution 1280x 720 12 bits , PCLK = 72MHz , Frame format(Line length x Frame length): 2388x 1004 30fps (This is included blanking time.)

use 4 sensors and each one link to UB913 and then to UB964 for one CSI-2 TX port output

And, your answer was:

> 2. I can't understand your issue well. do your camera have sensor and ISP both?

> if input data is 1280x720@30fps with RAW12 bit mode, the total payload rate is

> 331.776Mbps, which is much less than UB964 CSI2's 800Mbps/lane.

> The UB964's CSI2 output rate is fixed by REFCLK freq.

Should I need to consider blanking time for CSI-2 throughput in this case?

So, the throughput is 2338 x 1004 x 30fps x 12bit = 845Mbps?

Best Regards
Kenshow

over 7 years ago

0 Davor Glisic over 7 years ago

TI__Expert 8165 points

Hello-

There is no need to consider blanking time for the CSI-2 throughput.

Regards,
Davor

0 kenshow over 7 years ago in reply to Davor Glisic

Genius 3725 points

Hi

Thanks for your reply

Regards,
Kenshow

0 kenshow over 7 years ago in reply to kenshow

Genius 3725 points

Hi Davor,

I would like to reconfirm about CSI throughput ( lane rate ) about my case.
Another answer is is included blanking time for the lane rate as follows:

e2e.ti.com/.../2407048

I am confused whether it shuold be included the blanking time or not.
Which one is the correct answer?

Regards,
Kenshow

0 Davor Glisic over 7 years ago in reply to kenshow

TI__Expert 8165 points

Hello Ken,

I'm sorry for the confusion. The blanking time is not required for the 964 CSI throughput calculations. The following are sample calculations for the maximum bandwidth of the 964 CSI-2 interface:

Based on the above calculations, with the Hactive=1280 pixels, the maximum bandwidth of the 964 CSI-2 interface is between ~2.4 Gbps and ~3Gbps (600 Mbps - 750 Mbps per camera) depending on the type of the CSI-2 forwarding and whether the CSI clock is continuous or not.

Regards,

Davor

0 kenshow over 7 years ago in reply to Davor Glisic

Genius 3725 points

Hi Davor,

Thanks for your reply.
Unfortunately, I cannot see your attached file about sample calculation on previous post.
Please attach it, again.

Regards,
Kenshow

0 Davor Glisic over 7 years ago in reply to kenshow

TI__Expert 8165 points

Hello Ken,

Below is the attachment.

Regards,

Davor

DS90UB96x CSI Output Bandwidth.pdf

0 kenshow over 7 years ago in reply to Davor Glisic

Genius 3725 points

Hi Davor,

I could get the bandwidth document. Thanks.
And, I have a question about the document as blow:

What are Pkt_Overhead1/2?
Who define them?

Regards,
Kenshow

0 Davor Glisic over 7 years ago in reply to kenshow

TI__Expert 8165 points

Hello-

The Pkt_overhead is the CSI-2 packet timing overhead. If you reference Figure 6 in the 964 datasheet, the Pkt_overhead2 (with continuous clock) is the sum of the Low-Power to High-Speed Transition, HS-Zero, Start of Transmission, HS-Trail, and High-Speed to Low-Power Transmission times. The Pkt_overhead1 (without continuous clock) includes the overhead introduced by starting and stopping the CSI-2 clock. See Figure 7 in the datasheet. These figures come from the MIPI D-Phy spec.

Regards,
Davor

0 kenshow over 7 years ago in reply to Davor Glisic

Genius 3725 points

Hi Davor,

I'm sorry for the delay in my reply.
I have question about Figure 6 in data sheet.
Where is ”Ths-sync" defined?

Regards,
Kenshow

0 Davor Glisic over 7 years ago in reply to kenshow

TI__Expert 8165 points

Hello Ken,

The Ths-sync is the width of the 8-bit sync pattern: 00011101. In the MIPI Dphy spec, it is defined in a figure equivalent to Figure 6. Figure 6 in the 964 datasheet could be made more clear to indicate that the Ths-sync is 8-bits wide.

Regards,
Davor

0 kenshow over 7 years ago in reply to Davor Glisic

Genius 3725 points

Hi Davor,

I calculated Pkt_Overhead2 @800Mbps from your information, but it did not become the value you indicated. It is not 820 nsec.
What is wrong, right?
My calculation is:

UI INST 800Mbps 1.25 ns
TLPX 50 ns
THS-PREPARE+THS-ZERO 145+4*UI INST 157.5 ns
THS-SYNC 8*UI INST 10 ns
THS-TRAIL 60+4*UI INST 65 ns
THS-EXIT 100 ns
--------------------------------------------------------------------------
SUM 382.5 ns

Regards
Kenshow

0 Davor Glisic over 7 years ago in reply to kenshow

TI__Expert 8165 points

Hello Kenshow,

Some of the values you used from the MIPI DPHY standard are MIN values. The actual implementation of the design has some of the timing parameters that are greater than the MIN values. The values that I used in my calculations are the actual values from design simulations.

Regards,
Davor

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DS90UB964-Q1: Should I need to consider blanking time for CSI-2 throughput?