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DS90UB927Q-Q1: DS90UB927/UB924

Ian Wang
Mastermind 29710 points
Part Number: DS90UB927Q-Q1

Dear Guys,

Here is structure as customer application as below, READ/WRITE will abnormal  no matter UB927 communicate to UB924 or UB924 communicate to Slave device.

We think it should cause by i2c clock stretching and would like to check if it can be adjust by some way such as register setting….

Please refer to the below waveform.

It’s a i2c read operation to the remote slave device after UB924 where the i2c host is at the front of UB927.

As you can see, 40 usec and 60usec are the clock stretching period caused by SerDes TX. Could those stretching time be adjustable of the SerDes configuration?

Thanks,Ian.

  • 0
    TI__Mastermind 30515 points

    Ian,

    the 40us time duration is caused by Transmitter which is delayed due to the ACK signal from remote slave. so you can see the SCL available when ACK is arriving the I2C master.

    unfortunately, this clock stretching is required for bi-directional application. Please see i2c app. note, the clock stretching is one feature based on I2C protocol definition.

    http://www.ti.com/lit/an/snla131a/snla131a.pdf

    best regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    TI__Mastermind 29710 points

    Dear Steven,

    We’re clear about what i2c clock stretching does, and this feature is needed when there’s a slow I2C slave device on the bus. 

    Since the clock is stretched by SerDes TX (UB927), customer wondering to know is it possible to adjust the period of the stretching in the SerDes register configuration?

    In addition, the stretching period seems various as you can see in waveform, there have two different values (40u and 60u).

    We also like to know could this be controllable or not?

    Thanks, Ian

  • 0 in reply to Ian Wang
    TI__Mastermind 29710 points
    Guys,
    May I have your comments for it?
    Thanks,
  • 0 in reply to Ian Wang
    TI__Mastermind 30515 points
    Ian,
    I think we already answer your questions, to be simple:
    1. strecting time can't be reduce, it is dependent on the BC rate, ACK response, also some variation due to parallel sync. time.
    2. 40us or 60us is due to dynamic variation to combine the ACK signal into the back channel, also is dependent on the ACK response from I2C slave. unfortunately, we can reduce it. but fpd-link has the lower lattency compared with our competitors.

    best regards,
    Steven