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DP83822IF: PHY Software Reset (B15=1, Address 0x0000)

Hirotaka Matsumoto
Guru 27585 points
Part Number: DP83822IF

Hi all

Would you mind if we ask DP83822IF?

We would like to confirm the operation of PHY Software Reset (B15=1, Address 0x0000).

<Question1>
How long does it rquire that PHY returns to default condition? 
Is it the same as hardware reset(7.7 Timing Requirements, Reset Timing on the datasheet P11)?
About MDC communicatio, does it require 195ms(T2 : Post power-up stabilization time prior to MDC preamble for register accesses) after software reset?

There is the description "This bit is self cleared and has the same effect as Hardware reset pin." on 0x001F.
However, we could not judge it.

<Question2>
After software reset, will the register data of 0x0017(RMII and Status Register (RCSR)) return to default condition?

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Mastermind 18425 points
    Hello Matsumoto-san,

    It is difficult to accurately time software reset to normal operation because the software used will also have its own delay. The PHY takes 2ms from hardware reset before MDIO-MDC pins can be used. I would recommend using the same timing information for the software reset as well. Please ask customer to use some buffer to account for delay due to software.
    Register 0x1F bit 15 will reset the PHY, re-sample the straps, and bring all registers back to the default value on power-up. So any software configurations done after power-up will be lost.

    If reset is initiated by writing 0x8000 to register 0x1F then the straps will be resampled and register 0x17 will return to default condition.

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Guru 27585 points

    Aniruddha san

    Thank you so much for your reply.
    We are sorry that our questions were wrong.

    We would like to know follows;

    <Question1>
    Could you let us know the difference 0x001F bit15's reset(PHYRCR) and 0x0000 bit15's reset(BMCR)?

    <Question2>
    -We recognize that 0x001F bit15's reset(PHYRCR) is the similar with hardware reset.
     In case of 0x001F bit15's reset, we assume it is the same timing as hardware reset(7.7 Timing Requirements, Reset Timing on the datasheet P11).

    -About 0x0000 bit15's reset(BMCR), there is the description "Writing a 1 to this bit resets the PHY PCS registers."
     What does PCS register indicate?
     Does it mean address 0x3000 to 0x3002's PCS?
     In case of 0x0000 bit15's reset, we assume that it means PCS register's reset.
     So, it doesn't require the same timing as hardware reset(7.7 Timing Requirements, Reset Timing on the datasheet P11).
     How much is reset operation time and the release time(which returns to normal operation)?  

    We appreciate your help always.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    Guru 27585 points

    Aniruddha san

    We guess that your days are so busy, however could you let us know?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Aniruddha Khadye
    Guru 27585 points

    Hi team

    We guess that your days are so much busy, however could you give us the reply?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 23675 points

    Hi Matsumoto,

    A1:

    Register 0x0 reset will reset the PHY PCS layer but will not reset the PHY vendor specific register fields. It will not cause a reset to occur for HW bootstrap sampling.

    Register 0x1F reset is the same as the RESET pin and will cause all the registers to clear and re-sample the HW bootstraps.

    A2:

    Same timing for register 0x1F as is for RESET pin.

    A3:

    PCS means Physical Coding Sublayer.


  • 0 in reply to Ross Pimentel
    Guru 27585 points

    Ross san

    Thank you so much for your reply!

    OK, we got it!

    Kind regards,

    Hirotaka Matsumoto