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XIO2001: power up/power down sequencing

Part Number: XIO2001

Hello 

I have some questions to the power up/down sequencing as stated in the datasheet:

  • The datasheet does not specify a certain sequence for 1.5V and 3.3V rail. Is there any requirement to apply the rails at the same time/ within a certain minimum time frame? e.g. can I apply 3.3V first and after 10ms 1.5V?
  • Is it required to de-assert GRST# immediately after voltage rails are applied?
  • Does the bridge have an internal clock? Can the bridge also ramp up even without external REFCLK (initializing the bridge by an internal controller)?
  • When is the link training sequence starting? The datasheet says the following: 
    • The XIO2001 starts link training within 80 ms after PERST is deasserted
    • The bridge starts link training within 80 ms after GRST is deasserted

Thanks a lot for your support!