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TUSB1310A: UUSB1310A ULPI mode

vinayak koparkar
Prodigy 30 points

Part Number: TUSB1310A

I am interfacing USB controller with TUSB1310A on FPGA using ULPI interface in USB2.0 mode. After settings for strapping options, I started getting 60 MHz ulpi_clock and my link controller sends initial phy reset command followed by  command programming of register to set termselect, xcver & opmode correctly to the phy. I could see DP going HIGH from device side indicating device detect. But after that utmi_clock is getting suddenly stopped. What could be the reason for this ?  I am capturing UTMI signals on chipscope. 

My USB controoller ( form Synopsys ) is working and proven with UTMI mode and I am using it now in ULPI mode, where Synopsys ULPI wrapper is doing UTMI 2 ULPI conversion. I have run RTL simulaton with some other ULPI phy and that works correctly. Not understanding why TI USB phy suddenly stops utmi_clock. I am expecting SE0 inidication , followed by Chirp.  

Is there any bootcode exists for initial enumeration of TUSB1310A phy in ULPI mode ?

Thanks,

Vinayak.

  • 0
    TI__Expert 7395 points
    Hello Vinayak,

    The TUSB1310A is compliant with the ULPI specification, so there is no special bootcode designed exclusively for this device.

    I am forwarding your question internally hoping someone can shed some light on what the problem might be. Please forward me any additional debugging information that might help to narrow down the issue (Step by step procedure followed on the ULPI side, USB protocol analyzer traces, etc)

    Thanks,
    Jorge
  • 0 in reply to Jorge Llamas (SWAT)
    Prodigy 30 points

    My host controller is issuing below three register writes on ULPI interface and with that I see in RTL simulation , Chirp happens properly.In RTL simulation I used Synopsys ULPI phy model. Does TI PHY requires any additional or different programming ? Do you have TUSB1310A phy verilog model for RTL simulation ?  Any important timings/delay need to be followed between these register writes ?  On oscilloscope, I observed Chip happening but looks like Chirp gets timed out and it goes for FS mode. But even inn that first "getDescriptor" command fails.

    Do we need to wait for 1.4 ms PLL lock tie even before these reg writes ?

    85,60 

    84, 45

    84, 54 

    Thanks,

    Vinayak

  • 0 in reply to vinayak koparkar
    Prodigy 30 points
    Any feedback on this ? Is there ant verilog simulation model for TUSB 1310A PHY ?

    Thanks,
    Vinayak
  • 0 in reply to vinayak koparkar
    TI__Expert 7395 points
    Hello Vinayak,

    As mentioned before, the TUSB1310A is compliant with the ULPI specification, and as such, it doesn't require any additional or different programming. The only special considerations for the device are detailed on the errata document at www.ti.com/.../sllz063.pdf

    Unfortunately we do not have any Verilog model we can provide.

    Finally, please note that the TUSB1310A is not recommended for new designs.

    Regards,
    Jorge