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TPS65983B: FLASH SHARING and I2C ADDR FOR 6 DEVICES

Scott P
Prodigy 85 points
Part Number: TPS65983B
Other Parts Discussed in Thread: TPS65982

Both the TPS65983B and the TPS65986 us the I2C_ADDR pin to set the device as "SPI Owner, UART Master 0 (Primary)" or "UART Slave X" for x=[1..7], and sets the I2C address. (Table 10, Pg 80/74 )

In a design with six TPS6598x's, I need different I2C addresses to access the six devices. But, setting the I2C address to anything besides "Master" seems to require sharing the Flash via UART_RX/TX.

UART_TX is a CMOS output, so the slaves UART_TX'x can not be tied as a multi-drop. I can not find any documentation addressing how to connect more than two TPS6598x devices. Does the firmware support daisy chaining RX to TX in a loop of the six devices? Or how otherwise can this case be handled other than setting all devices as master with their own flash, and feeding all devices through an I2C switch?

Thank You.

  • 0
    TI__Mastermind 36756 points
    Hi Scott,

    The TPS65983B is only recommended for use with TBT systems that follow an Intel Reference Design.
    If you were to have 6 TPS65986's you could have 3 pairs that each have their own flash. Basically, you would have 3 SPI Flash chips and two TPS65986's connected through UART for each flash chip. Our FW would not work with booting up 6 TPS6598Xs through the same SPI Flash.

    Thank you,
    Eric
  • 0 in reply to Eric Beljaars
    Prodigy 85 points
    This approach does not resolve the issue that the three FLASH master devices will all have the same I2C address, 0x00 for a TPS65986, on which DEBUG_CTL1/2 do not set I2C_ADDR_B4/5, like the TPS65983B does. Also, since only B4 & B5 can be changed on a master, having six devices on the same I2C bus will require using master-slave pairs. It would be a preferable solution to use 86's each with their own flash, if they will boot from a flash when the I2C_ADDR is set to a value other than 0x0.

    The I2C address is not set until after the boot, and the documentation is conflicted on how master vs. slave boot is selected. Both the 86 and 83B description for SPI_MISO says "This pin is used during boot sequence to determine if the flash memory is valid." And Figure 60 (69 for 83B) shows the SPI_MISO pin state selecting "Load from SPI Flash" or "Download from UART". But Table 10 show that 0R to GND on I2C_ADDR sets the device as "SPI Owner, UART Master 0 (Primary)" and all other setting as "UART Slave."

    Q1) If six TPS65986's, each with a flash attached, are set to unique Table 10 I2C_ADDR values of 0x01 .. 0x06, will they boot from flash and properly operate as six different address slave devices on their I2C Port 1's?

    Q2) Exactly the same as Q1), except three pairs connected by UART_RX/TX and exactly one of each pair having a flash connected. None of the devices having I2C_ADDR 0R to G.

    The two roots being:
    will a device boot from a connected flash when I2C_ADDR does NOT have R0 to GND, and
    will a device with a connected flash supply firmware to another device over UART, if the device with the flash does NOT have I2C_ADDR 0R to GND?

    Thank You.
  • 0 in reply to Eric Beljaars
    Prodigy 85 points
    This approach does not solve the issue that the three FLASH master devices will all have the same I2C address, 0x00 for a TPS65986, on which DEBUG_CTL1/2 do not set I2C_ADDR_B4/5, like the TPS65983B does. Also, since only B4 & B5 can be changed on a master, having six devices on the same I2C bus will require using master-slave pairs. It would be a preferable solution to use 86's each with their own flash, if they will boot from a flash when the I2C_ADDR is set to a value other than 0x0.

    The I2C address is not set until after the boot, and the documentation is conflicted on how master vs. slave boot is selected. Both the 86 and 83B description for SPI_MISO says "This pin is used during boot sequence to determine if the flash memory is valid." And Figure 60 (69 for 83B) shows the SPI_MISO pin state selecting "Load from SPI Flash" or "Download from UART". But Table 10 show that 0R to GND on I2C_ADDR sets the device as "SPI Owner, UART Master 0 (Primary)" and all other setting as "UART Slave."

    1) If six TPS65986's, each with a flash attached, are set to unique Table 10 I2C_ADDR values of 0x01 .. 0x06, will they boot from flash and operate as six different address slave devices on their I2C Port 1's?

    2) Exactly the same as 1), except three pairs connected by UART_RX/TX and exactly one of each pair having a flash connected. None of the devices having I2C_ADDR 0R to G.

    The two roots being: will a device boot from a connected flash when I2C_ADDR does NOT have I2C_ADDR 0R to GND, and
    will a device with a connected flash supply firmware to another device over UART, if the device with the flash does NOT have I2C_ADDR 0R to GND?

    Thank You.
  • 0 in reply to Scott P
    TI__Mastermind 36756 points
    Hi Scott,

    1. This would work as expected, each of the 6 TPS65986's will boot from their own SPI Flash and the I2C address will be configured during the boot process.

    2. You are correct, this would not work with the TPS65986. You could also consider the TPS65982 as it determines the I2C address from the Debug_CTL1 and Debug_CTL2 pins as well. With the '82, you could probably share a SPI Flash between two of the PD controllers to cut down on the solution cost a bit.

    Thank you,
    Eric