• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 394 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83822I: About configuration delay time of TX_CLK

Satoshi
Guru 19645 points
Part Number: DP83822I

Please let me know about TX_CLK specification for DP83822 below;

①Is there limit for maximum TX_CLK delay time?

②I found two way to configure TX_CLK delay time, PCB design(Datasheet page-13 comment(13)) and resister setting(Datasheet page-64 TX Clock shift).

　If there the other way, please let me know.

③When ② have the other way, can this setting configure delay time in each step?

　if yes, how is the step width?

Best regards,

Satoshi

  • 0
    TI__Mastermind 18425 points
    Hello Satoshi,

    As per the RGMII standard the max value for TX_CLK delay is not specified.

    Currently internal delay and PCB delay are the only two ways to skew data and clock for RGMII application.

    The internal delay does not have steps, it is a fixed delay of 3.5ns.

    -Regards,
    Aniruddha