According to the documentation a read packet on the SPI bus to the device should go something like this:
Assert Slave Select
17-bit message on MOSI
Deassert Slave Select
Assert Slave Select
17-bit message on MISO
The master we are using only has the ability to put data on MOSI in multiples of 8, so the message on MOSI of a read request is 24-bits before we deassert slave select. What is the behavior of the device if more then 17 clock cycles lapse from the start of the MOSI message and the desassertion of the SS? Is it possible to communicate with the device from a master with this restriction?
I have tried to issue reads with 24-bit MOSI messages but the device starts to respond after 17-bits have been transmitted. The MISO response RW bit and address is correct but the data is incorrect. It is always the exact same data as was in the MOSI message.
