Hi,
I have a question about description of the datasheet.
VSYNC is described as below;
"3. 10-bit mode: VS restricted to no more than one transition per 10 PCLK cycles. "
Using a deserializer(914A), do we need to mind this restrict?
I'm supposing that this restriction is for the Serealizer(913A) side.
Best Regards,
Kuramochi
