DS90UB928Q-Q1: PDB rise before VDDIO ramping up

NOBUO FUJIHARA

Part Number: DS90UB928Q-Q1

Hi Champs,

My customer asked power-up sequence, please support.

Q.1)

When PDB set High several us earlier before VDD33 ramping up, if PDB is toggled Low to High after VDD33 ramping up, will the device correctly power-up?

Q.2)

In Talbe 10 "Power-Up Sequencing Constrains", t3 is defined as 0.05ms< t3 < 1.5ms.

Is there any concern if PDB set High later than 1.5ms after VDD3 ramping-up?

Best regards,

over 7 years ago

0 Davor Glisic over 7 years ago

TI__Expert 8145 points

Hello-

1. Yes. Wait for 1-2 ms before toggling the PDB. Also, when toggling the PDB, the PDB must be held low for at least 2ms.
2. In Table 10, t3 is defined as the VDD33 rise time.

Regards,
Davor

0 NOBUO FUJIHARA over 7 years ago in reply to Davor Glisic

TI__Genius 9335 points

Thanks for the answer.

For Q.2, I see t3 is rise time. So VDD3 does have to rise within 1.5ms for correct power-up sequence, doesn't it?

Best regards,

0 Davor Glisic over 7 years ago in reply to NOBUO FUJIHARA

TI__Expert 8145 points

That's correct.

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DS90UB928Q-Q1: PDB rise before VDDIO ramping up