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TCA8418: GPIO_DAT_STAT# "Read these twice to clear them"???

John Child
Intellectual 600 points
Part Number: TCA8418
Other Parts Discussed in Thread: TCA9555

The TCA8418 data sheet says:-

8.6.2.8 GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0x14–0x16)

These registers show the GPIO state when read for inputs and outputs. Read these twice to clear them

Can someone please explain what "Read these twice to clear them" means in this context.

I was thinking/hoping that they would just reflect the current input status when configured as GPIO inputs.

  • 0
    TI__Guru* 75681 points

    Hey John,

    Unfortunately I have not had a chance yet to play with this device in the lab yet (just ordered some but need to get a test set up for it) however the datasheet does seem to indicate that the GPIOs are scanned every 25ms and from my understanding they check the previous value read to see if the state of the pin has changed (likely using two flipflops to store this data). If the previous state and current state are both the same (both low for example) then the device will conclude the button was pressed (not flucuating/bouncing) and move the data into the FIFO. This logic was meant for the keypad mode of the device.

    Using it in as a general purpose input makes me assume the device should store the last value previously scanned and the current value.

    Thanks,

    -Bobby

    3/19/18 (Monday)
  • 0 in reply to BOBBY
    Intellectual 600 points
    Hi Bobby,

    If we use this chip in our design we would be configuring all GPIOs as inputs. (No matrix, no scanning, just to get extra PIOs, a bit of debounce, limited ESD protection and the pull ups).

    From the description in 8.6.2.15 (Debounce Disable Registers) I thought we would have ~50 uSecs of debounce in GPIO only mode. 25 mSecs would be too much latency for our application so I really appreciate any more light you can shed on this register and any latency to expect when used in GPIO input mode.

    Thanks
    John
  • 0 in reply to John Child
    TI__Guru* 75681 points

    Hey John,

    "From the description in 8.6.2.15 (Debounce Disable Registers) I thought we would have ~50 uSecs of debounce in GPIO only mode."

    Debounce time seems to be a maximum of 60ms. I would probably trust this section of the datasheet. As stated previously, I do believe the values in the register will be a delayed value of the last two scans (25ms apart so the maximum delay would be 50ms if I understand correctly). It may be better to look at our IO expanders as it seems the delayed values may not be ideal for your application.

    We do have IO expanders that have ESD protection and internal pull ups. One example would be the TCA9555 with 100k internal pull ups and ESD protection of 2k HBM and 1k CDM. Several package options and device is default set as inputs without the need to configure the registers like the TCA8418 would require. The only thing it doesn't have is the debounce feature.

    You can find other I/O Expanders here:

    Be sure to look for the TCA family as they are more cost competitive and fix some of the bugs that PCA line up had.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    Intellectual 600 points

    Bobby,

    Thanks for the references. Now that we are clear that we do not need/want matrix we will look at other chips.

    John