Hi there,
We have used SN65DSI84 in our design. In the first version we did not do swapping of channel A and channel and nor we did the order reversal on any of the channels. With this configuration our design was working fine.
In the next revision of the design, we did the channel swapping for odd and even pixels. And also did the order reversal on Channel A. We set the register 0x0A to 0x63. We have set the value of register at 0x28 to 0x31. With these configuration we are seeing a big lag in the frame rate of the display. thr frame rate is getting dropped to a very low value. We get error logs on the processor side, saying that the VSYNC is not received bt the DSI controller.
We have connected two sn65sdi84 devices to two dsi ports of the processor. Each DSI port is feeding 1920x1080p data to each sn65dsi device.
Can you please suggest us the steps to identify the reason of Vsync not getting received by DSI port and how to tune the delay timing parameter of sn65dsi84
Thanks,
Nimesh Kotak
