TCA9617A: TCA9617 - I2C Problem

Hi Lucas,
I use B version.
I have some difficulties in using the chip at 800k (at 400k it works well). Is there any specific thing (rather the pull-up resistors value) I should double check for this device?
BTW should I use the same pull-up resistor's value for both sides of the chip?
Thanks,
Shlomi

Hey Shlomi,

Can you post o-scope shots of the waveforms on both sides (SDA1/SCL1 and SDA2/SCL2), that may give us a better idea of what is going on.

What is the slave device you are trying to communicate with? (does it support fast mode plus?)

"BTW should I use the same pull-up resistor's value for both sides of the chip?"
-The pull up resistor depends on the bus capacitance. You can see in the equation of the app note on how to select a pull up resistor that the bus capacitance dictate the max pull up resistor allowable.

Thanks,
-Bobby

Hi Bobby,

The attached file includes snap-shots taken from my board.

The file names imply their content: MS means Master while SL means Slave, Tr applies for Rise Time, Tf for Fall time and PD applies for Propagation delay.

The basic set-up includes Aardvark device as a Master (3.3V) and my device as a Slave (1.8V).

My pull-up resistors in both sides are:2K.

Please take a look at the snap-shots and send me your analysis/recommendations.

Thanks,

Shlomi

Valens TCA9617.docx

I to c.zip

Hey Shlomi,

"Please take a look at the snap-shots and send me your analysis/recommendations."

1) In your SCL_SL_tr picture I do see the signal jittering a bit, likely just noise though it does look like it could peak around 100mV.
2) The rise times on your waveforms look fine so the pull up resistors seem to be a good value.
3) The undershoot in some of your pictures (looks to go to a max value of -0.5V) is likely due to the strong pull down of the master. This plus parasitic inductance (from wires) is likely causing the problem due to inductive kickback from such a fast change in voltage over a small amount of time. The signal integrity does not look to be affected by this however the negative swing could potentially cause damage to our device as our absolute minimum value allowed on the I2C bus is -0.5V. A shorter cable connecting to J17 could also help.
4) I do see something odd occur in the i2c_ms_setup picture. The data line looks like its getting pulled low from the opposite side. I am assuming this is an ACK otherwise something wrong is occuring. Please see request below (A):

A) Can you send me pictures of a full transaction? (it should include the start condition followed by 9 clock pulses and the SDA line) I would look to see pictures from both A side and then B side of the device (2 pictures: one from A and one from B).

Thanks,
-Bobby

Hi Bobby,
Thanks for the answer.
The basic problem is ability to forward short data and inability to forward long data.
I tried to shorten the Aardvark cable with no success in solving the problem.
Asuming I have noise problem which is the preferred solution? Adding capacitots?? On which side?
When I return to work I'll send you the needed snap-shot.
Thanks,
Shlomi

Hey Sholomi,

Double checking on you here, were you able to get additional snap shots of communication?

Also, I did not see your additional questions until just now, sorry about that.

"Asuming I have noise problem which is the preferred solution? Adding capacitots?? On which side?"
-I don't think the 100mV jitter is causing the issue here. The best solution is to use an LDO as a power source though that is not always an option. The next best thing could be to add capacitance however I don't think that is necessary and you are limited by the amount of capacitance allowed by I2C standard. I would leave this alone until we can get a better picture.

"The basic problem is ability to forward short data and inability to forward long data."
-It could be possible the SDA/SCL lines are out of sync with each other...... I would need to see wave forms to confirm.

I also tried to find a datasheet on your Valens device but I wasn't able to find it. Are you able to provide a copy?

Thanks,
-Bobby

Hey Shlomi,

I have not heard back from you in about a week so I assume you were able to resolve the issue. I have gone and marked Lucas's original reply to this post as the suggested answer as it does answer your original question.

If you are still seeing issues, please open up a new thread and we can discuss this further.

Thanks,
-Bobby

Hi Bobby,

I worked on this issue and found that when adding 47 pf capacitors from SDA/ SCL signals to GND (MS or SL side) can fix the problem.

Yet I have some problems while making clock stretching.

Is there known issue  here?

I will continue in making the debug but it will be helpful if you can send your advise.

Is there any restriction in using 2 TCA9617B devices "back to back" as appears in the attached drawing?

BTW -  I still have some problems while using the TCA9617B device.

Thanks,

Shlomi

TCA9617B.docx

Shlomi,

"Yet I have some problems while making clock stretching.

Is there known issue  here?"

-I have not seen issues due to clock stretching.

"Is there any restriction in using 2 TCA9617B devices "back to back" as appears in the attached drawing?"

-B side of both devices cannot be contact with each other.

-At 1.8V, you can't have B side connected to this pull up rail as the voltage offset of B side would be around 0.52V while ViL for 1.8V logic is 0.54V. B side could potentially be larger than the ViL so it would not work.

For this to work you would need to have both A sides connected to the 1.8V side.

Is there any reason for you to use this configuration?

"BTW -  I still have some problems while using the TCA9617B device."

Do you have scopeshots (9~18 clock pulses) with SDA and SCL in the same pictures when you are seeing issues that you can provide?

-Bobby

Hi Bobby,

Thank you for the answer.

Please find below a few remarks:

1       The 1.8V connection is done in the A side while the 3.3V connection is done in the B side

2        Since the 'back to back ' connection is done in both A sides can it work properly? I doing it as part of my debug process.

3        If I would like to make 'back to back ' connection at the B sides (3.3v) will it work well?

4        In my tests I using Aardvark devices. Have you made such tests (with Aardvark,at 800KHz speed) as well?

 

Thanks,

Shlomi

Shlomi,

"2 Since the 'back to back ' connection is done in both A sides can it work properly? I doing it as part of my debug process."
- Yes, A side connected to each other will work.

"3 If I would like to make 'back to back ' connection at the B sides (3.3v) will it work well?"
- This is NOT recommended in the datasheet and could cause issues with contention (such as in an ACK event)

"4 In my tests I using Aardvark devices. Have you made such tests (with Aardvark,at 800KHz speed) as well?"
- I have not used the arrdvark device.

-Bobby

Hi Bobby,

Just for being sure everything is clear please write down in which of the 2 cases the set-up can work well? (please refer to the 2 drawings attached).

BTW the drawings include also the used voltages and the sides for each connection (A and B of the level shifter).

Thanks,

Shlomi

TCA9617BV.docx

Hi Bobby,

Do you mean that the over set-up can't work properly?

Thanks,

Shlomi

Hey Shlomi,

No, the picture uploaded is the correct set up. (It is the set up that will work).

-Bobby