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DS92LV2422: Internal clock

NAOKI AOYAMA
Guru 11215 points
Part Number: DS92LV2422


Hello,

Our customer use the DS92LV2422, have a question.

The customer use the DS92LV2422 with 75MHz parallel clock.

The DS92LV2422 receive a 1.05GHz serial data and internal PLL circuit locked 75MHz.

How about the maximum internal clock for read serial data? Is it 1.05GHz ? or 2.1GHz?

Best Regards,

Naoki Aoyama

  • 0
    TI__Mastermind 35130 points
    Hi Naoki,

    It shouldn't matter whether it's 1.05GHz or 2.1GHz, as that just means it's either reading data in on only the rising edge, or it's reading data in on the rising edge and the falling edge. But that is an internal process and shouldn't matter to the customer. Is there a reason why they care about it?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Guru 11215 points
    Hello I.K.,

    Thank you for your reply.
    Perhaps, the customer consider EMI noise.
    So, they want to know how much the internal peak clock frequency.

    Regards,
    Naoki Aoyama
  • 0 in reply to NAOKI AOYAMA
    TI__Mastermind 35130 points
    Hi Naoki,

    Sorry for the late reply, I have received the below information about your inquiry:

    The internal clock is 28*Pclk. The serial data is traveling at 28 x Pixel CLK, and the clock signal is embedded within the serial stream. A distinct “stop bit” and “start bit” repeats every 28 serial bits to indicate the embedded clock. If the serial rate is 1.05 GHz, this is equivalent to a 2.1 Gbps signal. If you take 2.1 Gbps/28 = 75 Mbps for the parallel data. This indicates the deserialized data rate. The output pixel clock of the DS92LV2422 for this rate is 75 MHz (i.e maximum clock rate), since the clock uses either the rising or falling edge (DDR clocking is not supported by any of the Channel Link devices).

    Do you have more information from the customer about the purpose of the question? How does this relate to EMI considerations?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Guru 11215 points
    Hello I.K.,

    Thank you for your reply.
    The customer are during the design phase now.
    So, they are trying to prevent EMI noise.

    Thanks,
    Naoki Aoyama