XIO3130: Bitween EP and EP communication on XIO3130

user559927

Part Number: XIO3130

Hello,
Please advise regarding XIO3130 below,

My System configration:
RC(RootComplexPCIe)---XIO3130 UP(upstream)port
EP0 (EndPointPCIe Device)---XIO3130 DN1(downsteam)port
EP1 (EndPointPCIe Device)---XIO3130 DN2(downsteam)port

Is it possible to communicate bitween EP0 and EP1 directly?
For examle, EP0's DMAC(PCIe master) directly access(read/write) to EP1's
memory(PCIe slave).

over 7 years ago

0 Yaser Ibrahim over 7 years ago

TI__Genius 10250 points

Hello,

We will look into this and get back to you.

Regards,
Yaser

0 Charley Cai over 7 years ago

TI__Genius 12866 points

Hello,

It is possible to communicate between EP0 and EP1 directly. XIO3130 supports peer to peer communication. You can refer to PCIE specification for more detail.

Best Regards,

Charley Cai

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XIO3130: Bitween EP and EP communication on XIO3130